HSIO Power Management Configuration Reg 5 (MODPHY_PM_CFG5) – Offset 10d0 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

HSIO Power Management Configuration Reg 5 (MODPHY_PM_CFG5) – Offset 10d0

Bit Range	Default	Access	Field Name and Description
31:0	0h	RW	Controller SPD RTD3 Request [26:0] (MSPDRTREQ) This field represents ASL code trigger request for ModPHY SPD gating. If this bit is set (to 1) for a controller, it implies that ASL code provides consent for SPD to be gated for the corresponding controllers lanes. Note that this bit could also be more statically used by BIOS to set this to 1 for a controller where SPD will only be managed through other interfaces implying ASL code does not exist for a controller. This is not a POR mode of operation if a function is enabled ASL code will exist for all controllers that are enabled. However, the controllers that are not enabled (Function Disabled), this field will be statically set by BIOS to activate ASL component in SPD gating equations. Bit 0: Corresponds to PCIe Controller A, Function 0 Bit 1: Corresponds to PCIe Controller A, Function 1 Bit 2: Corresponds to PCIe Controller A, Function 2 Bit 3: Corresponds to PCIe Controller A, Function 3 Bit 4: Corresponds to PCIe Controller B, Function 0 Bit 5: Corresponds to PCIe Controller B, Function 1 Bit 6: Corresponds to PCIe Controller B, Function 2 Bit 7: Corresponds to PCIe Controller B, Function 3 Bit 8: Corresponds to PCIe Controller C, Function 0 Bit 9: Corresponds to PCIe Controller C, Function 1 Bit 10: Corresponds to PCIe Controller C, Function 2 Bit 11: Corresponds to PCIe Controller C, Function 3 Bit 12: Corresponds to SATA Controller Bit 13: Corresponds to Gbe Controller Bit 14: Corresponds to xHCI Controller Bit 15: Corresponds to xDCI Controller Bit 16: Corresponds to UFS Controller Bit 17: Corresponds to PCIe Controller D, Function 0 Bit 18: Corresponds to PCIe Controller D, Function 1 Bit 19: Corresponds to PCIe Controller D, Function 2 Bit 20: Corresponds to PCIe Controller D, Function 3 Bit 21: Corresponds to PCIe Controller E, Function 0 Bit 22: Corresponds to PCIe Controller E, Function 1 Bit 23: Corresponds to PCIe Controller E, Function 2 Bit 24: Corresponds to PCIe Controller E, Function 3 Bit 25: Corresponds to DMI Controller Bit 26: Corresponds to UFS Controller 2 Bit 27: Corresponds to PCIe Controller F, Function 0 Bit 28: Corresponds to PCIe Controller F, Function 1 Bit 29: Corresponds to PCIe Controller F, Function 2 Bit 30: Corresponds to PCIe Controller F, Function 3 Bit 31: Corresponds to GBETSN Controller

Bit Range

Default

Access

Field Name and Description

31:0

Controller SPD RTD3 Request [26:0] (MSPDRTREQ)

This field represents ASL code trigger request for ModPHY SPD gating. If this bit is set (to 1) for a controller, it implies that ASL code provides consent for SPD to be gated for the corresponding controllers lanes.

Note that this bit could also be more statically used by BIOS to set this to 1 for a controller where SPD will only be managed through other interfaces implying ASL code does not exist for a controller.

This is not a POR mode of operation if a function is enabled ASL code will exist for all controllers that are enabled. However, the controllers that are not enabled (Function Disabled), this field will be statically set

by BIOS to activate ASL component in SPD gating equations.

Bit 0: Corresponds to PCIe Controller A, Function 0

Bit 1: Corresponds to PCIe Controller A, Function 1

Bit 2: Corresponds to PCIe Controller A, Function 2

Bit 3: Corresponds to PCIe Controller A, Function 3

Bit 4: Corresponds to PCIe Controller B, Function 0

Bit 5: Corresponds to PCIe Controller B, Function 1

Bit 6: Corresponds to PCIe Controller B, Function 2

Bit 7: Corresponds to PCIe Controller B, Function 3

Bit 8: Corresponds to PCIe Controller C, Function 0

Bit 9: Corresponds to PCIe Controller C, Function 1

Bit 10: Corresponds to PCIe Controller C, Function 2

Bit 11: Corresponds to PCIe Controller C, Function 3

Bit 12: Corresponds to SATA Controller

Bit 13: Corresponds to Gbe Controller

Bit 14: Corresponds to xHCI Controller

Bit 15: Corresponds to xDCI Controller

Bit 16: Corresponds to UFS Controller

Bit 17: Corresponds to PCIe Controller D, Function 0

Bit 18: Corresponds to PCIe Controller D, Function 1

Bit 19: Corresponds to PCIe Controller D, Function 2

Bit 20: Corresponds to PCIe Controller D, Function 3

Bit 21: Corresponds to PCIe Controller E, Function 0

Bit 22: Corresponds to PCIe Controller E, Function 1

Bit 23: Corresponds to PCIe Controller E, Function 2

Bit 24: Corresponds to PCIe Controller E, Function 3

Bit 25: Corresponds to DMI Controller

Bit 26: Corresponds to UFS Controller 2

Bit 27: Corresponds to PCIe Controller F, Function 0

Bit 28: Corresponds to PCIe Controller F, Function 1

Bit 29: Corresponds to PCIe Controller F, Function 2

Bit 30: Corresponds to PCIe Controller F, Function 3

Bit 31: Corresponds to GBETSN Controller