I2C Enable (IC_ENABLE) – Offset 6c - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
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GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
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- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
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SPI PCI Configuration
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THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

I2C Enable (IC_ENABLE) – Offset 6c

Bit Range	Default	Access	Field Name and Description
31:19	0h	RO	Reserved (RSVD_IC_ENABLE_2)
18	0h	RO	Reserved (RSVD_SMBUS_ALERT_EN)
17	0h	RO	Reserved (RSVD_SMBUS_SUSPEND_EN)
16	0h	RO	Reserved (RSVD_SMBUS_CLK_RESET)
15:4	0h	RO	Reserved (RSVD_IC_ENABLE_1)
3	0h	RO	Reserved (RSVD_SDA_STUCK_RECOVERY_ENABLE)
2	0h	RW	TX_CMD_BLOCK (TX_CMD_BLOCK)
1	0h	RW	ABORT (ABORT) Sofware can abort I2C transfer by setting this bit. Hw will clear this ABORT bit once the STOP has been detected.
0	0h	RW	ENABLE (ENABLE) Controls whether the controller is enabled. 0: Disables I2C controller(TX and RX FIFOs are held in an erased state) 1: Enables I2C controller. Software can disable the controller while it is active. However, it is important that care be taken to ensure that the controller is disabled properly. When the controller is disabled, the following occurs: -The TX FIFO and RX FIFO get flushed. -Status bits in the IC_INTR_STAT register are still active until the controller goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the controller stops the current transfer at the end of the current byte and does not acknowledge the transfer.

I2C Status (IC_STATUS)

Clear GEN_CALL Interrupt (IC_CLR_GEN_CALL) I2C Status (IC_STATUS)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

I2C Enable (IC_ENABLE) – Offset 6c