I2C Target Address (IC_TAR) – Offset 4 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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xDCI PCI Configuration

I2C Target Address (IC_TAR) – Offset 4

The register should only be updated when the I2C is not enabled (IC_ENABLE=0) or No Master mode operations are active (IC_STATUS[5] = 0 and IC_CON[0] = 1 and IC_STATUS[2] = 1).

Bit Range	Default	Access	Field Name and Description
31:17	0h	RO	Reserved (RSVD_IC_TAR_2)
16	0h	RO	Reserved (RSVD_SMBUS_QUICK_CMD)
15:14	0h	RO	Reserved (RSVD_IC_TAR_1)
13	0h	RO	Reserved (RSVD_DEVICE_ID)
12	1h	RW	IC_10BITADDR_MASTER (IC_10BITADDR_MASTER) This bit controls whether the I2C starts its transfers in 7-or 10-bit addressing mode when acting as a master. 0: 7 bit addressing 1: 10-bit addressing
11	0h	RW	SPECIAL (SPECIAL) This bit indicates whether software performs a General Call or START BYTE command. 0: ignore bit 10 GC_OR_START and use IC_TAR normally. 1: perform special I2C command as specified in GC_OR_START bit
10	0h	RW	GC_OR_START (GC_OR_START) If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the I2C. 0: General Call Address after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The I2C remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. 1: START BYTE
9:0	55h	RW	IC_TAR (IC_TAR) This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. Note: If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and target device, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a device.

I2C High Speed Master Mode Code Address (IC_HS_MADDR)

I2C Control (IC_CON) I2C High Speed Master Mode Code Address (IC_HS_MADDR)