Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID Date Version Classification
834576 10/10/2024 001 Public
Document Table of Contents
Document Table of Contents
Introduction CNVi WiFi* PCI Configuration eSPI PCI Configuration eSPI PCR GPIO Commumity 0 GPIO Commumity 1 GPIO Commumity 2 GPIO Commumity 3 GPIO Commumity 4 GPIO Commumity 5 GSPI Additional MMIO GSPI DMA GSPI MMIO GSPI PCI Configuration I2C Additional MMIO I2C DMA I2C MMIO I3C / I2C / UART / GSPI PCR I3C Additional MMIO I3C DMA I3C MMIO I3C PCI Configuration IDE-Redirect (IDE-R) PCI Configuration Integrated GbE PCI Configuration Integrated Sensor Hub (ISH) MMIO Integrated Sensor Hub (ISH) PCI Configuration Intel(R) Management Engine Interface (MEI) MMIO Intel(R) Management Engine Interface (MEI) PCI Configuration Intel® High Definition Audio MMIO Intel® High Definition Audio PCI Configuration Intergrated GbE MMIO Keyboard and Text (KT) PCI Configuration P2SB PCI Configuration PCIe* PCI Configuration PMC I/O Based PMC MMIO PMC PCI Configuration PMC SSRAM PCI Configuration RTC Index RTC PCR SATA ABAR SATA AIDPBA SATA Initialization (SIR) Index SATA MXPBA SATA MXTBA SATA PCI Configuration SATA Port 0 ABAR SATA Port 1 ABAR SATA Port 2 ABAR SATA Port 3 ABAR SATA Port 4 ABAR SATA Port 5 ABAR SATA Port 6 ABAR SATA Port 7 ABAR SMBus MMIO and I/O SMBus PCI Configuration SMBus PCR SMBus TCO I/O SPI MMIO SPI PCI Configuration THC MMIO Common THC MMIO Port THC PCI Configuration UART Additional MMIO UART DMA UART MMIO UART PCI Configuration USB MMIO USB PCI Configuration xDCI MMIO Device xDCI MMIO Global xDCI PCI Configuration
Introduction
CNVi WiFi* PCI Configuration
CNVi WiFi* PCI Configuration Vendor and Device ID (VEN_DEV_ID) Device Command and Status (PCI_COM_STAT) Class Code and Revision ID (PCI_CLASS_CODE) Base Address Register BAR0 Low (BAR0) Base Address Register BAR0 High (BAR1) Sub System Identification (SUBSYS_ID) Capabilities Pointer (CAP_PTR) Interrupt (INTERRUPT) PCI Express Capabilities (GIO_CAP) Device Capabilities (GIO_DEV_CAP) Device Control Register (GIO_DEV) Device Control 2 (GIO_DEV_CAP_2) Device Control (GIO_DEV_2) MSIX Capability (MSIX_CAP_HEAD) MSIX Capability Structure (MSIX_TABLE_OFFSET) MSIX Capability Structure (MSIX_PBA_OFFSET) Power Management Capabilities (PMC) Power Management Capabilities (PMCSR) Capability ID and Message Control (MSI_MSG_CTRL) MSI Low Address (MSI_LOW_ADD) MSI High Address (MSI_HIGH_ADD) MSI Data (MSI_DATA) Uncorrectable Error Severity (UNCORRECT_ERR_SEV) CORRECT Error Status (CORRECT_ERR_STAT) CORRECT Error MASK (CORRECT_ERR_MASK) Advanced Error Capabilities and Control (ADVANCED_ERR_CAP) Header Log 1 (HEADER_LOG1) Header Log 2 (HEADER_LOG2) Header Log 3 (HEADER_LOG3) Header Log 4 (HEADER_LOG4) Device Serial Number Capability (GIO_SERIAL_CAP) Serial Number Low (GIO_SERIAL_LOW) Serial Number Upper (GIO_SERIAL_UP) L1 substates Extended Capability Header (L1PM_SUB_EXTND_CAP_HEAD) L1 Substates Capability (L1PM_SUB_CAP) L1 Substates Control (L1PM_SUB_CNTRL) L1 Substates Control 2 (L1PM_SUB_CNTRL2) Vendor Specific Capability Header (VEN_SPEC_CAP) Vendor Specific Extended Capability (VEN_SPEC_EXTND_CAP) SW LTR Pointer (LTP_PTR) DevIdle Pointer (DEV_IDLE_PTR) DevIdle Power on Latency (DEV_IDLE_PWR)
Vendor and Device ID (VEN_DEV_ID)
Device Command and Status (PCI_COM_STAT)
Class Code and Revision ID (PCI_CLASS_CODE)
Base Address Register BAR0 Low (BAR0)
Base Address Register BAR0 High (BAR1)
Sub System Identification (SUBSYS_ID)
Capabilities Pointer (CAP_PTR)
Interrupt (INTERRUPT)
PCI Express Capabilities (GIO_CAP)
Device Capabilities (GIO_DEV_CAP)
Device Control Register (GIO_DEV)
Device Control 2 (GIO_DEV_CAP_2)
Device Control (GIO_DEV_2)
MSIX Capability (MSIX_CAP_HEAD)
MSIX Capability Structure (MSIX_TABLE_OFFSET)
MSIX Capability Structure (MSIX_PBA_OFFSET)
Power Management Capabilities (PMC)
Power Management Capabilities (PMCSR)
Capability ID and Message Control (MSI_MSG_CTRL)
MSI Low Address (MSI_LOW_ADD)
MSI High Address (MSI_HIGH_ADD)
MSI Data (MSI_DATA)
Uncorrectable Error Severity (UNCORRECT_ERR_SEV)
CORRECT Error Status (CORRECT_ERR_STAT)
CORRECT Error MASK (CORRECT_ERR_MASK)
Advanced Error Capabilities and Control (ADVANCED_ERR_CAP)
Header Log 1 (HEADER_LOG1)
Header Log 2 (HEADER_LOG2)
Header Log 3 (HEADER_LOG3)
Header Log 4 (HEADER_LOG4)
Device Serial Number Capability (GIO_SERIAL_CAP)
Serial Number Low (GIO_SERIAL_LOW)
Serial Number Upper (GIO_SERIAL_UP)
L1 substates Extended Capability Header (L1PM_SUB_EXTND_CAP_HEAD)
L1 Substates Capability (L1PM_SUB_CAP)
L1 Substates Control (L1PM_SUB_CNTRL)
L1 Substates Control 2 (L1PM_SUB_CNTRL2)
Vendor Specific Capability Header (VEN_SPEC_CAP)
Vendor Specific Extended Capability (VEN_SPEC_EXTND_CAP)
SW LTR Pointer (LTP_PTR)
DevIdle Pointer (DEV_IDLE_PTR)
DevIdle Power on Latency (DEV_IDLE_PWR)
eSPI PCI Configuration
eSPI PCI Configuration Device and Vendor Identifiers (ESPI_DID_VID) Device Status and Command (ESPI_STS_CMD) Class Code and Revision ID (ESPI_CC_RID) Peripheral Channel Header Type and Primary Latency (ESPI_PCHT_PCPLT) Sub System Identifiers (ESPI_SS) Capability List Pointer (ESPI_CAPP) I/O Decode Ranges and I/O Enables (ESPI_IOD_IOE) eSPI Generic IO Range 1 (ESPI_LGIR1) eSPI Generic IO Range 2 (ESPI_LGIR2) eSPI Generic IO Range 3 (ESPI_LGIR3) eSPI Generic IO Range 4 (ESPI_LGIR4) USB Legacy Keyboard/Mouse Control (ESPI_ULKMC) eSPI Generic Memory Range (ESPI_LGMR) eSPI CS1 IO Routing Enables (ESPI_CS1IORE) eSPI CS1 Generic IO Range 1 (ESPI_CS1GIR1) eSPI CS1 Generic Memory Range 1 (ESPI_CS1GMR1) BIOS Decode Enable (ESPI_BDE) BIOS Control (ESPI_BC) eSPI IO Routing Enables for ESPI CS2 (ESPI_IORE_EXT[2]) eSPI Generic IO Range 1 for ESPI CS2 (ESPI_GIR1_EXT[2]) eSPI Generic Memory Range 1 for ESPI CS2 (ESPI_GMR1_EXT[2]) eSPI IO Routing Enables for ESPI CS3 (ESPI_IORE_EXT[3]) eSPI Generic IO Range 1 for ESPI CS3 (ESPI_GIR1_EXT[3]) eSPI Generic Memory Range 1 for ESPI CS3 (ESPI_GMR1_EXT[3])
Device and Vendor Identifiers (ESPI_DID_VID)
Device Status and Command (ESPI_STS_CMD)
Class Code and Revision ID (ESPI_CC_RID)
Peripheral Channel Header Type and Primary Latency (ESPI_PCHT_PCPLT)
Sub System Identifiers (ESPI_SS)
Capability List Pointer (ESPI_CAPP)
I/O Decode Ranges and I/O Enables (ESPI_IOD_IOE)
eSPI Generic IO Range 1 (ESPI_LGIR1)
eSPI Generic IO Range 2 (ESPI_LGIR2)
eSPI Generic IO Range 3 (ESPI_LGIR3)
eSPI Generic IO Range 4 (ESPI_LGIR4)
USB Legacy Keyboard/Mouse Control (ESPI_ULKMC)
eSPI Generic Memory Range (ESPI_LGMR)
eSPI CS1 IO Routing Enables (ESPI_CS1IORE)
eSPI CS1 Generic IO Range 1 (ESPI_CS1GIR1)
eSPI CS1 Generic Memory Range 1 (ESPI_CS1GMR1)
BIOS Decode Enable (ESPI_BDE)
BIOS Control (ESPI_BC)
eSPI IO Routing Enables for ESPI CS2 (ESPI_IORE_EXT[2])
eSPI Generic IO Range 1 for ESPI CS2 (ESPI_GIR1_EXT[2])
eSPI Generic Memory Range 1 for ESPI CS2 (ESPI_GMR1_EXT[2])
eSPI IO Routing Enables for ESPI CS3 (ESPI_IORE_EXT[3])
eSPI Generic IO Range 1 for ESPI CS3 (ESPI_GIR1_EXT[3])
eSPI Generic Memory Range 1 for ESPI CS3 (ESPI_GMR1_EXT[3])
eSPI PCR
eSPI PCR eSPI Device Configuration Register and Link Control (SLV_CFG_REG_CTL) eSPI Device Configuration Register Data (SLV_CFG_REG_DATA) Peripheral Channel Error for ESPI Device 0 (PCERR_SLV0) Peripheral Channel Error for ESPI Second Device (PCERR_SLV1) Virtual Wire Channel Error for eSPI First Device (VWERR_SLV0) Virtual Wire Channel Error for eSPI Second Device (VWERR_SLV1) Flash Access Channel Error for eSPI First Device (FCERR_SLV0) Link Error for eSPI First Device (LNKERR_SLV0) Link Error for eSPI Second Device (LNKERR_SLV1) Generic GPIO upstream VW Enables for eSPI First Device (VWGPIO_IN_EN_SLV[0]) Generic GPIO upstream VW Enables for eSPI Second Device (VWGPIO_IN_EN_SLV[1]) Generic GPIO downstream VW Enables for eSPI First Device (VWGPIO_OUT_EN_SLV[0]) Generic GPIO Downstream VW Enables for eSPI Second Device (VWGPIO_OUT_EN_SLV[1]) Generic GPIO VW control (VWGPIO_CTL) Peripheral Channel Error for ESPI Third Device (PCERR_SLV_EXT[2]) Virtual Channel Error for ESPI Third Device (VWERR_SLV_EXT[2]) Link Error for ESPI Third Device (LNKERR_SLV_EXT[2]) Generic GPIO Upstream VW Enables for eSPI Third Device (VWGPIO_IN_EN_SLV_EXT[2]) Generic GPIO Downstream VW Enables for eSPI Third Device (VWGPIO_OUT_EN_SLV_EXT[2]) Peripheral Channel Error for ESPI Fourth Device (PCERR_SLV_EXT[3]) Virtual Channel Error for ESPI Fourth Device 3 (VWERR_SLV_EXT[3]) Link Error for ESPI Fourth Device (LNKERR_SLV_EXT[3]) Generic GPIO Upstream VW Enables for eSPI Fourth Device (VWGPIO_IN_EN_SLV_EXT[3]) Generic GPIO Downstream VW Enables for eSPI Fourth Device (VWGPIO_OUT_EN_SLV_EXT[3])
eSPI Device Configuration Register and Link Control (SLV_CFG_REG_CTL)
eSPI Device Configuration Register Data (SLV_CFG_REG_DATA)
Peripheral Channel Error for ESPI Device 0 (PCERR_SLV0)
Peripheral Channel Error for ESPI Second Device (PCERR_SLV1)
Virtual Wire Channel Error for eSPI First Device (VWERR_SLV0)
Virtual Wire Channel Error for eSPI Second Device (VWERR_SLV1)
Flash Access Channel Error for eSPI First Device (FCERR_SLV0)
Link Error for eSPI First Device (LNKERR_SLV0)
Link Error for eSPI Second Device (LNKERR_SLV1)
Generic GPIO upstream VW Enables for eSPI First Device (VWGPIO_IN_EN_SLV[0])
Generic GPIO upstream VW Enables for eSPI Second Device (VWGPIO_IN_EN_SLV[1])
Generic GPIO downstream VW Enables for eSPI First Device (VWGPIO_OUT_EN_SLV[0])
Generic GPIO Downstream VW Enables for eSPI Second Device (VWGPIO_OUT_EN_SLV[1])
Generic GPIO VW control (VWGPIO_CTL)
Peripheral Channel Error for ESPI Third Device (PCERR_SLV_EXT[2])
Virtual Channel Error for ESPI Third Device (VWERR_SLV_EXT[2])
Link Error for ESPI Third Device (LNKERR_SLV_EXT[2])
Generic GPIO Upstream VW Enables for eSPI Third Device (VWGPIO_IN_EN_SLV_EXT[2])
Generic GPIO Downstream VW Enables for eSPI Third Device (VWGPIO_OUT_EN_SLV_EXT[2])
Peripheral Channel Error for ESPI Fourth Device (PCERR_SLV_EXT[3])
Virtual Channel Error for ESPI Fourth Device 3 (VWERR_SLV_EXT[3])
Link Error for ESPI Fourth Device (LNKERR_SLV_EXT[3])
Generic GPIO Upstream VW Enables for eSPI Fourth Device (VWGPIO_IN_EN_SLV_EXT[3])
Generic GPIO Downstream VW Enables for eSPI Fourth Device (VWGPIO_OUT_EN_SLV_EXT[3])
GPIO Commumity 0
GPIO Commumity 0 Family Base Address (FAMBAR) Pad Base Address (PADBAR) Miscellaneous Configuration (MISCCFG) Pad Ownership (PAD_OWN_GPP_D_0) Pad Ownership (PAD_OWN_GPP_D_1) Pad Ownership (PAD_OWN_GPP_D_2) Pad Ownership (PAD_OWN_GPP_R_0) Pad Ownership (PAD_OWN_GPP_R_1) Pad Ownership (PAD_OWN_GPP_J_0) Pad Ownership (PAD_OWN_GPP_J_1) Pad Ownership (PAD_OWN_GPP_J_2) Pad Configuration Lock (PADCFGLOCK_GPP_D_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_D_0) Pad Configuration Lock (PADCFGLOCK_GPP_R_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_R_0) Pad Configuration Lock (PADCFGLOCK_GPP_J_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_J_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_D_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_R_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_J_0) GPI Interrupt Status (GPI_IS_GPP_D_0) GPI Interrupt Status (GPI_IS_GPP_R_0) GPI Interrupt Status (GPI_IS_GPP_J_0) GPI Interrupt Enable (GPI_IE_GPP_D_0) GPI Interrupt Enable (GPI_IE_GPP_R_0) GPI Interrupt Enable (GPI_IE_GPP_J_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_D_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_R_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_J_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_D_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_R_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_0) SMI Status (GPI_SMI_STS_GPP_D_0) SMI Enable (GPI_SMI_EN_GPP_D_0) NMI Status (GPI_NMI_STS_GPP_D_0) NMI Enable (GPI_NMI_EN_GPP_D_0) GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET) GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET) GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET) GPIO Hardware Information NMI Int Offset (NMI_INT_OFFSET) GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_D) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_R) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_J) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_13) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_13) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_14) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_14) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_15) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_15) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_16) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_16) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_17) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_17) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_18) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_18) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_19) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_19) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_20) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_20) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_21) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_21) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_22) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_22) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_23) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_23) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_13) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_13) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_14) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_14) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_15) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_15) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_16) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_16)
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_GPP_D_0)
Pad Ownership (PAD_OWN_GPP_D_1)
Pad Ownership (PAD_OWN_GPP_D_2)
Pad Ownership (PAD_OWN_GPP_R_0)
Pad Ownership (PAD_OWN_GPP_R_1)
Pad Ownership (PAD_OWN_GPP_J_0)
Pad Ownership (PAD_OWN_GPP_J_1)
Pad Ownership (PAD_OWN_GPP_J_2)
Pad Configuration Lock (PADCFGLOCK_GPP_D_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_D_0)
Pad Configuration Lock (PADCFGLOCK_GPP_R_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_R_0)
Pad Configuration Lock (PADCFGLOCK_GPP_J_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_J_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_D_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_R_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_J_0)
GPI Interrupt Status (GPI_IS_GPP_D_0)
GPI Interrupt Status (GPI_IS_GPP_R_0)
GPI Interrupt Status (GPI_IS_GPP_J_0)
GPI Interrupt Enable (GPI_IE_GPP_D_0)
GPI Interrupt Enable (GPI_IE_GPP_R_0)
GPI Interrupt Enable (GPI_IE_GPP_J_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_D_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_R_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_J_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_D_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_R_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_0)
SMI Status (GPI_SMI_STS_GPP_D_0)
SMI Enable (GPI_SMI_EN_GPP_D_0)
NMI Status (GPI_NMI_STS_GPP_D_0)
NMI Enable (GPI_NMI_EN_GPP_D_0)
GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET)
GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET)
GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET)
GPIO Hardware Information NMI Int Offset (NMI_INT_OFFSET)
GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET)
GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_D)
GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_R)
GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_J)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_17)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_19)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_20)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_20)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_21)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_21)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_22)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_22)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_23)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_23)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_16)
GPIO Commumity 1
GPIO Commumity 1 Family Base Address (FAMBAR) Pad Base Address (PADBAR) Miscellaneous Configuration (MISCCFG) Pad Ownership (PAD_OWN_GPP_A_0) Pad Ownership (PAD_OWN_GPP_A_1) Pad Ownership (PAD_OWN_GPP_B_0) Pad Ownership (PAD_OWN_GPP_B_1) Pad Ownership (PAD_OWN_GPP_B_2) Pad Configuration Lock (PADCFGLOCK_GPP_A_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_A_0) Pad Configuration Lock (PADCFGLOCK_GPP_B_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_B_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_A_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_B_0) GPI Interrupt Status (GPI_IS_GPP_A_0) GPI Interrupt Status (GPI_IS_GPP_B_0) GPI Interrupt Enable (GPI_IE_GPP_A_0) GPI Interrupt Enable (GPI_IE_GPP_B_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_B_0) SMI Status (GPI_SMI_STS_GPP_B_0) SMI Enable (GPI_SMI_EN_GPP_B_0) NMI Status (GPI_NMI_STS_GPP_B_0) NMI Enable (GPI_NMI_EN_GPP_B_0) GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET) GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET) GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET) GPIO Hardware Information NMI Int Offset (NMI_INT_OFFSET) GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_A) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_B) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_13) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_13) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_13) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_13) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_14) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_14) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_15) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_15) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_16) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_16) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_17) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_17) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_18) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_18) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_19) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_19) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_20) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_20) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_21) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_21)
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_GPP_A_0)
Pad Ownership (PAD_OWN_GPP_A_1)
Pad Ownership (PAD_OWN_GPP_B_0)
Pad Ownership (PAD_OWN_GPP_B_1)
Pad Ownership (PAD_OWN_GPP_B_2)
Pad Configuration Lock (PADCFGLOCK_GPP_A_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_A_0)
Pad Configuration Lock (PADCFGLOCK_GPP_B_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_B_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_A_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_B_0)
GPI Interrupt Status (GPI_IS_GPP_A_0)
GPI Interrupt Status (GPI_IS_GPP_B_0)
GPI Interrupt Enable (GPI_IE_GPP_A_0)
GPI Interrupt Enable (GPI_IE_GPP_B_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_B_0)
SMI Status (GPI_SMI_STS_GPP_B_0)
SMI Enable (GPI_SMI_EN_GPP_B_0)
NMI Status (GPI_NMI_STS_GPP_B_0)
NMI Enable (GPI_NMI_EN_GPP_B_0)
GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET)
GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET)
GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET)
GPIO Hardware Information NMI Int Offset (NMI_INT_OFFSET)
GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET)
GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_A)
GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_B)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_17)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_19)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_20)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_20)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_21)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_21)
GPIO Commumity 2
GPIO Commumity 2 Family Base Address (FAMBAR) Pad Base Address (PADBAR) Miscellaneous Configuration (MISCCFG) Pad Ownership (PAD_OWN_DSW_0) Pad Ownership (PAD_OWN_DSW_1) Pad Configuration Lock (PADCFGLOCK_DSW_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_DSW_0) Host Software Pad Ownership (HOSTSW_OWN_DSW_0) GPI Interrupt Status (GPI_IS_DSW_0) GPI Interrupt Enable (GPI_IE_DSW_0) GPI General Purpose Events Status (GPI_GPE_STS_DSW_0) GPI General Purpose Events Enable (GPI_GPE_EN_DSW_0) GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET) GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET) GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET) GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET) GPIO Hardware Information Register Group (REGISTER_GROUP_DSW) Pad Configuration DW0 (PAD_CFG_DW0_GPD_0) Pad Configuration DW1 (PAD_CFG_DW1_GPD_0) Pad Configuration DW0 (PAD_CFG_DW0_GPD_1) Pad Configuration DW1 (PAD_CFG_DW1_GPD_1) Pad Configuration DW0 (PAD_CFG_DW0_GPD_2) Pad Configuration DW1 (PAD_CFG_DW1_GPD_2) Pad Configuration DW0 (PAD_CFG_DW0_GPD_3) Pad Configuration DW1 (PAD_CFG_DW1_GPD_3) Pad Configuration DW0 (PAD_CFG_DW0_GPD_4) Pad Configuration DW1 (PAD_CFG_DW1_GPD_4) Pad Configuration DW0 (PAD_CFG_DW0_GPD_5) Pad Configuration DW1 (PAD_CFG_DW1_GPD_5) Pad Configuration DW0 (PAD_CFG_DW0_GPD_6) Pad Configuration DW1 (PAD_CFG_DW1_GPD_6) Pad Configuration DW0 (PAD_CFG_DW0_GPD_7) Pad Configuration DW1 (PAD_CFG_DW1_GPD_7) Pad Configuration DW0 (PAD_CFG_DW0_GPD_8) Pad Configuration DW1 (PAD_CFG_DW1_GPD_8) Pad Configuration DW0 (PAD_CFG_DW0_GPD_9) Pad Configuration DW1 (PAD_CFG_DW1_GPD_9) Pad Configuration DW0 (PAD_CFG_DW0_GPD_10) Pad Configuration DW1 (PAD_CFG_DW1_GPD_10) Pad Configuration DW0 (PAD_CFG_DW0_GPD_11) Pad Configuration DW1 (PAD_CFG_DW1_GPD_11) Pad Configuration DW0 (PAD_CFG_DW0_GPD_12) Pad Configuration DW1 (PAD_CFG_DW1_GPD_12)
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_DSW_0)
Pad Ownership (PAD_OWN_DSW_1)
Pad Configuration Lock (PADCFGLOCK_DSW_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_DSW_0)
Host Software Pad Ownership (HOSTSW_OWN_DSW_0)
GPI Interrupt Status (GPI_IS_DSW_0)
GPI Interrupt Enable (GPI_IE_DSW_0)
GPI General Purpose Events Status (GPI_GPE_STS_DSW_0)
GPI General Purpose Events Enable (GPI_GPE_EN_DSW_0)
GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET)
GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET)
GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET)
GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET)
GPIO Hardware Information Register Group (REGISTER_GROUP_DSW)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_12)
GPIO Commumity 3
GPIO Commumity 3 Family Base Address (FAMBAR) Pad Base Address (PADBAR) Miscellaneous Configuration (MISCCFG) Pad Ownership (PAD_OWN_GPP_C_0) Pad Ownership (PAD_OWN_GPP_C_1) Pad Ownership (PAD_OWN_GPP_C_2) Pad Ownership (PAD_OWN_GPP_H_0) Pad Ownership (PAD_OWN_GPP_H_1) Pad Ownership (PAD_OWN_GPP_H_2) Pad Configuration Lock (PADCFGLOCK_GPP_C_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_C_0) Pad Configuration Lock (PADCFGLOCK_GPP_H_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_H_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_C_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_H_0) GPI Interrupt Status (GPI_IS_GPP_C_0) GPI Interrupt Status (GPI_IS_GPP_H_0) GPI Interrupt Enable (GPI_IE_GPP_C_0) GPI Interrupt Enable (GPI_IE_GPP_H_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_H_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_H_0) SMI Status (GPI_SMI_STS_GPP_C_0) SMI Enable (GPI_SMI_EN_GPP_C_0) NMI Status (GPI_NMI_STS_GPP_C_0) NMI Enable (GPI_NMI_EN_GPP_C_0) GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET) GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET) GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET) GPIO Hardware Information NMI Int Offset (NMI_INT_OFFSET) GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_C) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_H) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_13) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_13) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_14) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_14) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_15) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_15) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_16) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_16) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_17) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_17) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_18) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_18) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_19) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_19) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_20) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_20) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_21) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_21) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_22) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_22) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_23) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_23) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_13) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_13) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_14) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_14) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_15) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_15) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_16) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_16) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_17) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_17) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_18) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_18) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_19) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_19)
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_GPP_C_0)
Pad Ownership (PAD_OWN_GPP_C_1)
Pad Ownership (PAD_OWN_GPP_C_2)
Pad Ownership (PAD_OWN_GPP_H_0)
Pad Ownership (PAD_OWN_GPP_H_1)
Pad Ownership (PAD_OWN_GPP_H_2)
Pad Configuration Lock (PADCFGLOCK_GPP_C_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_C_0)
Pad Configuration Lock (PADCFGLOCK_GPP_H_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_H_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_C_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_H_0)
GPI Interrupt Status (GPI_IS_GPP_C_0)
GPI Interrupt Status (GPI_IS_GPP_H_0)
GPI Interrupt Enable (GPI_IE_GPP_C_0)
GPI Interrupt Enable (GPI_IE_GPP_H_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_H_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_H_0)
SMI Status (GPI_SMI_STS_GPP_C_0)
SMI Enable (GPI_SMI_EN_GPP_C_0)
NMI Status (GPI_NMI_STS_GPP_C_0)
NMI Enable (GPI_NMI_EN_GPP_C_0)
GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET)
GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET)
GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET)
GPIO Hardware Information NMI Int Offset (NMI_INT_OFFSET)
GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET)
GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_C)
GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_H)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_17)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_19)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_20)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_20)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_21)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_21)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_22)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_22)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_23)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_23)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_17)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_19)
GPIO Commumity 4
GPIO Commumity 4 Family Base Address (FAMBAR) Pad Base Address (PADBAR) Miscellaneous Configuration (MISCCFG) Pad Ownership (PAD_OWN_GPP_S_0) Pad Ownership (PAD_OWN_GPP_E_0) Pad Ownership (PAD_OWN_GPP_E_1) Pad Ownership (PAD_OWN_GPP_E_2) Pad Ownership (PAD_OWN_GPP_K_0) Pad Ownership (PAD_OWN_GPP_K_1) Pad Ownership (PAD_OWN_GPP_F_0) Pad Ownership (PAD_OWN_GPP_F_1) Pad Ownership (PAD_OWN_GPP_F_2) Pad Configuration Lock (PADCFGLOCK_GPP_S_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_S_0) Pad Configuration Lock (PADCFGLOCK_GPP_E_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_E_0) Pad Configuration Lock (PADCFGLOCK_GPP_K_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_K_0) Pad Configuration Lock (PADCFGLOCK_GPP_F_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_F_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_S_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_E_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_K_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_F_0) GPI Interrupt Status (GPI_IS_GPP_S_0) GPI Interrupt Status (GPI_IS_GPP_E_0) GPI Interrupt Status (GPI_IS_GPP_K_0) GPI Interrupt Status (GPI_IS_GPP_F_0) GPI Interrupt Enable (GPI_IE_GPP_S_0) GPI Interrupt Enable (GPI_IE_GPP_E_0) GPI Interrupt Enable (GPI_IE_GPP_K_0) GPI Interrupt Enable (GPI_IE_GPP_F_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_S_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_E_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_K_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_S_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_E_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_K_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_0) SMI Status (GPI_SMI_STS_GPP_E_0) SMI Enable (GPI_SMI_EN_GPP_E_0) NMI Status (GPI_NMI_STS_GPP_E_0) NMI Enable (GPI_NMI_EN_GPP_E_0) GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET) GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET) GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET) GPIO Hardware Information NMI Int Offset (NMI_INT_OFFSET) GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_S) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_E) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_K) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_F) PWM Control (PWMC) GPIO Serial Blink Enable (GP_SER_BLINK) GPIO Serial Blink Command/Status (GP_SER_CMDSTS) GPIO Serial Blink Data (GP_SER_DATA) GSX Controller Capabilities (GSX_CAP) GSX Channel-0 Capabilities DW0 (GSX_C0CAP_DW0) GSX Channel-0 Capabilities DW1 (GSX_C0CAP_DW1) GSX Channel-0 GP Input Level DW0 (GSX_C0GPILVL_DW0) GSX Channel-0 GP Input Level DW1 (GSX_C0GPILVL_DW1) GSX Channel-0 GP Output Level DW0 (GSX_C0GPOLVL_DW0) GSX Channel-0 GP Output Level DW1 (GSX_C0GPOLVL_DW1) GSX Channel-0 Command (GSX_C0CMD) GSX Channel-0 Test Mode (GSX_C0TM) Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_13) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_13) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_14) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_14) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_15) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_15) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_16) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_16) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_17) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_17) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_18) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_18) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_19) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_19) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_20) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_20) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_21) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_21) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_13) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_13) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_14) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_14) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_15) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_15) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_16) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_16) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_17) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_17) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_18) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_18) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_19) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_19) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_20) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_20) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_21) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_21) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_22) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_22) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_23) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_23)
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_GPP_S_0)
Pad Ownership (PAD_OWN_GPP_E_0)
Pad Ownership (PAD_OWN_GPP_E_1)
Pad Ownership (PAD_OWN_GPP_E_2)
Pad Ownership (PAD_OWN_GPP_K_0)
Pad Ownership (PAD_OWN_GPP_K_1)
Pad Ownership (PAD_OWN_GPP_F_0)
Pad Ownership (PAD_OWN_GPP_F_1)
Pad Ownership (PAD_OWN_GPP_F_2)
Pad Configuration Lock (PADCFGLOCK_GPP_S_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_S_0)
Pad Configuration Lock (PADCFGLOCK_GPP_E_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_E_0)
Pad Configuration Lock (PADCFGLOCK_GPP_K_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_K_0)
Pad Configuration Lock (PADCFGLOCK_GPP_F_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_F_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_S_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_E_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_K_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_F_0)
GPI Interrupt Status (GPI_IS_GPP_S_0)
GPI Interrupt Status (GPI_IS_GPP_E_0)
GPI Interrupt Status (GPI_IS_GPP_K_0)
GPI Interrupt Status (GPI_IS_GPP_F_0)
GPI Interrupt Enable (GPI_IE_GPP_S_0)
GPI Interrupt Enable (GPI_IE_GPP_E_0)
GPI Interrupt Enable (GPI_IE_GPP_K_0)
GPI Interrupt Enable (GPI_IE_GPP_F_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_S_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_E_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_K_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_S_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_E_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_K_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_0)
SMI Status (GPI_SMI_STS_GPP_E_0)
SMI Enable (GPI_SMI_EN_GPP_E_0)
NMI Status (GPI_NMI_STS_GPP_E_0)
NMI Enable (GPI_NMI_EN_GPP_E_0)
GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET)
GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET)
GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET)
GPIO Hardware Information NMI Int Offset (NMI_INT_OFFSET)
GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET)
GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_S)
GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_E)
GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_K)
GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_F)
PWM Control (PWMC)
GPIO Serial Blink Enable (GP_SER_BLINK)
GPIO Serial Blink Command/Status (GP_SER_CMDSTS)
GPIO Serial Blink Data (GP_SER_DATA)
GSX Controller Capabilities (GSX_CAP)
GSX Channel-0 Capabilities DW0 (GSX_C0CAP_DW0)
GSX Channel-0 Capabilities DW1 (GSX_C0CAP_DW1)
GSX Channel-0 GP Input Level DW0 (GSX_C0GPILVL_DW0)
GSX Channel-0 GP Input Level DW1 (GSX_C0GPILVL_DW1)
GSX Channel-0 GP Output Level DW0 (GSX_C0GPOLVL_DW0)
GSX Channel-0 GP Output Level DW1 (GSX_C0GPOLVL_DW1)
GSX Channel-0 Command (GSX_C0CMD)
GSX Channel-0 Test Mode (GSX_C0TM)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_17)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_19)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_20)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_20)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_21)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_21)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_17)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_19)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_20)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_20)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_21)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_21)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_22)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_22)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_23)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_23)
GPIO Commumity 5
GPIO Commumity 5 Family Base Address (FAMBAR) Pad Base Address (PADBAR) Miscellaneous Configuration (MISCCFG) Pad Ownership (PAD_OWN_GPP_I_0) Pad Ownership (PAD_OWN_GPP_I_1) Pad Ownership (PAD_OWN_GPP_I_2) Pad Configuration Lock (PADCFGLOCK_GPP_I_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_I_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_I_0) GPI Interrupt Status (GPI_IS_GPP_I_0) GPI Interrupt Enable (GPI_IE_GPP_I_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_I_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_I_0) SMI Status (GPI_SMI_STS_GPP_I_0) SMI Enable (GPI_SMI_EN_GPP_I_0) NMI Status (GPI_NMI_STS_GPP_I_0) NMI Enable (GPI_NMI_EN_GPP_I_0) GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET) GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET) GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET) GPIO Hardware Information NMI Int Offset (NMI_INT_OFFSET) GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_I) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_13) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_13) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_14) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_14) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_15) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_15) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_16) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_16)
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_GPP_I_0)
Pad Ownership (PAD_OWN_GPP_I_1)
Pad Ownership (PAD_OWN_GPP_I_2)
Pad Configuration Lock (PADCFGLOCK_GPP_I_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_I_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_I_0)
GPI Interrupt Status (GPI_IS_GPP_I_0)
GPI Interrupt Enable (GPI_IE_GPP_I_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_I_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_I_0)
SMI Status (GPI_SMI_STS_GPP_I_0)
SMI Enable (GPI_SMI_EN_GPP_I_0)
NMI Status (GPI_NMI_STS_GPP_I_0)
NMI Enable (GPI_NMI_EN_GPP_I_0)
GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET)
GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET)
GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET)
GPIO Hardware Information NMI Int Offset (NMI_INT_OFFSET)
GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET)
GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_I)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_16)
GSPI Additional MMIO
GSPI Additional MMIO Clock Configuration (CLOCKS) Resets (RESETS) Active LTR (ACTIVELTR_VALUE) Idle LTR (IDLELTR_VALUE) Tx Byte Count (TX_BIT_COUNT) Rx Byte Count (RX_BIT_COUNT) REG SSP_REG (SSP_REG) SPI CS Control (SPI_CS_CONTROL) Scratchpad Register 0 (SW_SCRATCH_0) Scratchpad Register 1 (SW_SCRATCH_1) Scratchpad Register 2 (SW_SCRATCH_2) Scratchpad Register 3 (SW_SCRATCH_3) Clock Gate (CLOCK_GATE) Address Low (REMAP_ADDR_LO) Address High (REMAP_ADDR_HI) Device Idle Control (DEVIDLE_CONTROL) Delayed Rx Clock (DEL_RX_CLK) Capabilities (CAPABLITIES)
Clock Configuration (CLOCKS)
Resets (RESETS)
Active LTR (ACTIVELTR_VALUE)
Idle LTR (IDLELTR_VALUE)
Tx Byte Count (TX_BIT_COUNT)
Rx Byte Count (RX_BIT_COUNT)
REG SSP_REG (SSP_REG)
SPI CS Control (SPI_CS_CONTROL)
Scratchpad Register 0 (SW_SCRATCH_0)
Scratchpad Register 1 (SW_SCRATCH_1)
Scratchpad Register 2 (SW_SCRATCH_2)
Scratchpad Register 3 (SW_SCRATCH_3)
Clock Gate (CLOCK_GATE)
Address Low (REMAP_ADDR_LO)
Address High (REMAP_ADDR_HI)
Device Idle Control (DEVIDLE_CONTROL)
Delayed Rx Clock (DEL_RX_CLK)
Capabilities (CAPABLITIES)
GSPI DMA
GSPI DMA DMA Transfer Source Address Low 0 (SAR_LO0) DMA Transfer Source Address High 0 (SAR_HI0) DMA Transfer Destination Address Low 0 (DAR_LO0) DMA Transfer Destination Address High 0 (DAR_HI0) Linked List Pointer Low 0 (LLP_LO0) Linked List Pointer High 0 (LLP_HI0) Control Register Low 0 (CTL_LO0) Control Register High 0 (CTL_HI0) Source Status 0 (SSTAT0) Destination Status 0 (DSTAT0) Source Status Address Low 0 (SSTATAR_LO0) Source Status Address High 0 (SSTATAR_HI0) Destination Status Address Low 0 (DSTATAR_LO0) Destination Status Address High 0 (DSTATAR_HI0) DMA Transfer Configuration Low 0 (CFG_LO0) DMA Transfer Configuration High 0 (CFG_HI0) Source Gather 0 (SGR0) Destination Scatter 0 (DSR0) DMA Transfer Source Address Low 1 (SAR_LO1) DMA Transfer Source Address High 1 (SAR_HI1) DMA Transfer Destination Address Low 1 (DAR_LO1) DMA Transfer Destination Address High 1 (DAR_HI1) Linked List Pointer Low 1 (LLP_LO1) Linked List Pointer High 1 (LLP_HI1) Control Register Low 1 (CTL_LO1) Control Register High 1 (CTL_HI1) Source Status 1 (SSTAT1) Destination Status 1 (DSTAT1) Source Status Address Low 1 (SSTATAR_LO1) Source Status Address High 1 (SSTATAR_HI1) Destination Status Address Low 1 (DSTATAR_LO1) Destination Status Address High 1 (DSTATAR_HI1) DMA Transfer Configuration Low 1 (CFG_LO1) DMA Transfer Configuration High 1 (CFG_HI1) Source Gather 1 (SGR1) Destination Scatter 1 (DSR1) Raw Interrupt Status (RawTfr) Raw Status for Block Interrupts (RawBlock) Raw Status for Source Transaction Interrupts (RawSrcTran) Raw Status for Destination Transaction Interrupts (RawDstTran) Raw Status for Error Interrupts (RawErr) Status for Transfer Interrupts (StatusTfr) Status for Block Interrupts (StatusBlock) Status for Source Transaction Interrupts (StatusSrcTran) Status for Destination Transaction Interrupts (StatusDstTran) Status for Error Interrupts (StatusErr) Mask for Transfer Interrupts (MaskTfr) Mask for Block Interrupts (MaskBlock) Mask for Source Transaction Interrupts (MaskSrcTran) Mask for Destination Transaction Interrupts (MaskDstTran) Mask for Error Interrupts (MaskErr) Clear for Transfer Interrupts (ClearTfr) Clear for Block Interrupts (ClearBlock) Clear for Source Transaction Interrupts (ClearSrcTran) Clear for Destination Transaction Interrupts (ClearDstTran) Clear for Error Interrupts (ClearErr) Combined Status (StatusInt) DMA Configuration (DmaCfgReg) DMA Channel Enable (ChEnReg) Global DMA Configuration (GLOBAL_CFG)
DMA Transfer Source Address Low 0 (SAR_LO0)
DMA Transfer Source Address High 0 (SAR_HI0)
DMA Transfer Destination Address Low 0 (DAR_LO0)
DMA Transfer Destination Address High 0 (DAR_HI0)
Linked List Pointer Low 0 (LLP_LO0)
Linked List Pointer High 0 (LLP_HI0)
Control Register Low 0 (CTL_LO0)
Control Register High 0 (CTL_HI0)
Source Status 0 (SSTAT0)
Destination Status 0 (DSTAT0)
Source Status Address Low 0 (SSTATAR_LO0)
Source Status Address High 0 (SSTATAR_HI0)
Destination Status Address Low 0 (DSTATAR_LO0)
Destination Status Address High 0 (DSTATAR_HI0)
DMA Transfer Configuration Low 0 (CFG_LO0)
DMA Transfer Configuration High 0 (CFG_HI0)
Source Gather 0 (SGR0)
Destination Scatter 0 (DSR0)
DMA Transfer Source Address Low 1 (SAR_LO1)
DMA Transfer Source Address High 1 (SAR_HI1)
DMA Transfer Destination Address Low 1 (DAR_LO1)
DMA Transfer Destination Address High 1 (DAR_HI1)
Linked List Pointer Low 1 (LLP_LO1)
Linked List Pointer High 1 (LLP_HI1)
Control Register Low 1 (CTL_LO1)
Control Register High 1 (CTL_HI1)
Source Status 1 (SSTAT1)
Destination Status 1 (DSTAT1)
Source Status Address Low 1 (SSTATAR_LO1)
Source Status Address High 1 (SSTATAR_HI1)
Destination Status Address Low 1 (DSTATAR_LO1)
Destination Status Address High 1 (DSTATAR_HI1)
DMA Transfer Configuration Low 1 (CFG_LO1)
DMA Transfer Configuration High 1 (CFG_HI1)
Source Gather 1 (SGR1)
Destination Scatter 1 (DSR1)
Raw Interrupt Status (RawTfr)
Raw Status for Block Interrupts (RawBlock)
Raw Status for Source Transaction Interrupts (RawSrcTran)
Raw Status for Destination Transaction Interrupts (RawDstTran)
Raw Status for Error Interrupts (RawErr)
Status for Transfer Interrupts (StatusTfr)
Status for Block Interrupts (StatusBlock)
Status for Source Transaction Interrupts (StatusSrcTran)
Status for Destination Transaction Interrupts (StatusDstTran)
Status for Error Interrupts (StatusErr)
Mask for Transfer Interrupts (MaskTfr)
Mask for Block Interrupts (MaskBlock)
Mask for Source Transaction Interrupts (MaskSrcTran)
Mask for Destination Transaction Interrupts (MaskDstTran)
Mask for Error Interrupts (MaskErr)
Clear for Transfer Interrupts (ClearTfr)
Clear for Block Interrupts (ClearBlock)
Clear for Source Transaction Interrupts (ClearSrcTran)
Clear for Destination Transaction Interrupts (ClearDstTran)
Clear for Error Interrupts (ClearErr)
Combined Status (StatusInt)
DMA Configuration (DmaCfgReg)
DMA Channel Enable (ChEnReg)
Global DMA Configuration (GLOBAL_CFG)
GSPI MMIO
GSPI MMIO Control 0 (SSCR0) Control 1 (SSCR1) Status (SSSR) Data (SSDR) Time-Out (SSTO) Transmit FIFO (SITF) Receive FIFO (SIRF)
Control 0 (SSCR0)
Control 1 (SSCR1)
Status (SSSR)
Data (SSDR)
Time-Out (SSTO)
Transmit FIFO (SITF)
Receive FIFO (SIRF)
GSPI PCI Configuration
GSPI PCI Configuration Device Id And Vendor Id Register (DEVVENDID) Status And Command (STATUSCOMMAND) Revision Id And Class Code (REVCLASSCODE) Cache Line Latency Header And Bist (CLLATHEADERBIST) Base Address Register (BAR) Base Address Register High (BAR_HIGH) Base Address Register1 (BAR1) Base Address Register1 High (BAR1_HIGH) Subsystem Vendor And Subsystem Id (SUBSYSTEMID) Expansion Rom Base Address (EXPANSION_ROM_BASEADDR) Capabilities Pointer Register (CAPABILITYPTR) Interrupt Register (INTERRUPTREG) Power Management Capability Id (POWERCAPID) Power Management Control And Status Register (PMECTRLSTATUS) Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD) Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG) Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG) Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG) D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG) General Purpose Read Write Register1 (GEN_REGRW1) General Purpose Read Write Register2 (GEN_REGRW2) General Purpose Read Write Register3 (GEN_REGRW3) General Purpose Read Write Register4 (GEN_REGRW4) General Purpose Input Register (GEN_INPUT_REG)
Device Id And Vendor Id Register (DEVVENDID)
Status And Command (STATUSCOMMAND)
Revision Id And Class Code (REVCLASSCODE)
Cache Line Latency Header And Bist (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Subsystem Vendor And Subsystem Id (SUBSYSTEMID)
Expansion Rom Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer Register (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Capability Id (POWERCAPID)
Power Management Control And Status Register (PMECTRLSTATUS)
Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD)
Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG)
Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG)
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write Register1 (GEN_REGRW1)
General Purpose Read Write Register2 (GEN_REGRW2)
General Purpose Read Write Register3 (GEN_REGRW3)
General Purpose Read Write Register4 (GEN_REGRW4)
General Purpose Input Register (GEN_INPUT_REG)
I2C Additional MMIO
I2C Additional MMIO Reserved (Reserved0) Resets (RESETS) Active LTR (ACTIVELTR_VALUE) Idle LTR (IDLELTR_VALUE) TX ACK Counts (TX_ACK_COUNT) Rx Byte Count (RX_BYTE_COUNT) Interrupt Status for Tx Complete (TX_COMPLETE_INTR_STAT) Tx Complete Interrupt Clear (TX_COMPLETE_INTR_CLR) Scratchpad Register 0 (SW_SCRATCH_0) Scratchpad Register 1 (SW_SCRATCH_1) Scratchpad Register 2 (SW_SCRATCH_2) Scratchpad Register 3 (SW_SCRATCH_3) Clock Gate (CLOCK_GATE) Reserved (Reserved1) Address Low (REMAP_ADDR_LO) Address High (REMAP_ADDR_HI) Reserved (Reserved2) Device Idle Control (DEVIDLE_CONTROL) Capabilities (CAPABLITIES)
Reserved (Reserved0)
Resets (RESETS)
Active LTR (ACTIVELTR_VALUE)
Idle LTR (IDLELTR_VALUE)
TX ACK Counts (TX_ACK_COUNT)
Rx Byte Count (RX_BYTE_COUNT)
Interrupt Status for Tx Complete (TX_COMPLETE_INTR_STAT)
Tx Complete Interrupt Clear (TX_COMPLETE_INTR_CLR)
Scratchpad Register 0 (SW_SCRATCH_0)
Scratchpad Register 1 (SW_SCRATCH_1)
Scratchpad Register 2 (SW_SCRATCH_2)
Scratchpad Register 3 (SW_SCRATCH_3)
Clock Gate (CLOCK_GATE)
Reserved (Reserved1)
Address Low (REMAP_ADDR_LO)
Address High (REMAP_ADDR_HI)
Reserved (Reserved2)
Device Idle Control (DEVIDLE_CONTROL)
Capabilities (CAPABLITIES)
I2C DMA
I2C DMA DMA Transfer Source Address Low 0 (SAR_LO0) DMA Transfer Source Address High 0 (SAR_HI0) DMA Transfer Destination Address Low 0 (DAR_LO0) DMA Transfer Destination Address High 0 (DAR_HI0) Linked List Pointer Low 0 (LLP_LO0) Linked List Pointer High 0 (LLP_HI0) Control Register Low 0 (CTL_LO0) Control Register High 0 (CTL_HI0) Source Status 0 (SSTAT0) Destination Status 0 (DSTAT0) Source Status Address Low 0 (SSTATAR_LO0) Source Status Address High 0 (SSTATAR_HI0) Destination Status Address Low 0 (DSTATAR_LO0) Destination Status Address High 0 (DSTATAR_HI0) DMA Transfer Configuration Low 0 (CFG_LO0) DMA Transfer Configuration High 0 (CFG_HI0) Source Gather 0 (SGR0) Destination Scatter 0 (DSR0) DMA Transfer Source Address Low 1 (SAR_LO1) DMA Transfer Source Address High 1 (SAR_HI1) DMA Transfer Destination Address Low 1 (DAR_LO1) DMA Transfer Destination Address High 1 (DAR_HI1) Linked List Pointer Low 1 (LLP_LO1) Linked List Pointer High 1 (LLP_HI1) Control Register Low 1 (CTL_LO1) Control Register High 1 (CTL_HI1) Source Status 1 (SSTAT1) Destination Status 1 (DSTAT1) Source Status Address Low 1 (SSTATAR_LO1) Source Status Address High 1 (SSTATAR_HI1) Destination Status Address Low 1 (DSTATAR_LO1) Destination Status Address High 1 (DSTATAR_HI1) DMA Transfer Configuration Low 1 (CFG_LO1) DMA Transfer Configuration High 1 (CFG_HI1) Source Gather 1 (SGR1) Destination Scatter 1 (DSR1) Raw Interrupt Status (RawTfr) Raw Status for Block Interrupts (RawBlock) Raw Status for Source Transaction Interrupts (RawSrcTran) Raw Status for Destination Transaction Interrupts (RawDstTran) Raw Status for Error Interrupts (RawErr) Status for Transfer Interrupts (StatusTfr) Status for Block Interrupts (StatusBlock) Status for Source Transaction Interrupts (StatusSrcTran) Status for Destination Transaction Interrupts (StatusDstTran) Status for Error Interrupts (StatusErr) Mask for Transfer Interrupts (MaskTfr) Mask for Block Interrupts (MaskBlock) Mask for Source Transaction Interrupts (MaskSrcTran) Mask for Destination Transaction Interrupts (MaskDstTran) Mask for Error Interrupts (MaskErr) Clear for Transfer Interrupts (ClearTfr) Clear for Block Interrupts (ClearBlock) Clear for Source Transaction Interrupts (ClearSrcTran) Clear for Destination Transaction Interrupts (ClearDstTran) Clear for Error Interrupts (ClearErr) Combined Status (StatusInt) DMA Configuration (DmaCfgReg) DMA Channel Enable (ChEnReg) Global DMA Configuration (GLOBAL_CFG)
DMA Transfer Source Address Low 0 (SAR_LO0)
DMA Transfer Source Address High 0 (SAR_HI0)
DMA Transfer Destination Address Low 0 (DAR_LO0)
DMA Transfer Destination Address High 0 (DAR_HI0)
Linked List Pointer Low 0 (LLP_LO0)
Linked List Pointer High 0 (LLP_HI0)
Control Register Low 0 (CTL_LO0)
Control Register High 0 (CTL_HI0)
Source Status 0 (SSTAT0)
Destination Status 0 (DSTAT0)
Source Status Address Low 0 (SSTATAR_LO0)
Source Status Address High 0 (SSTATAR_HI0)
Destination Status Address Low 0 (DSTATAR_LO0)
Destination Status Address High 0 (DSTATAR_HI0)
DMA Transfer Configuration Low 0 (CFG_LO0)
DMA Transfer Configuration High 0 (CFG_HI0)
Source Gather 0 (SGR0)
Destination Scatter 0 (DSR0)
DMA Transfer Source Address Low 1 (SAR_LO1)
DMA Transfer Source Address High 1 (SAR_HI1)
DMA Transfer Destination Address Low 1 (DAR_LO1)
DMA Transfer Destination Address High 1 (DAR_HI1)
Linked List Pointer Low 1 (LLP_LO1)
Linked List Pointer High 1 (LLP_HI1)
Control Register Low 1 (CTL_LO1)
Control Register High 1 (CTL_HI1)
Source Status 1 (SSTAT1)
Destination Status 1 (DSTAT1)
Source Status Address Low 1 (SSTATAR_LO1)
Source Status Address High 1 (SSTATAR_HI1)
Destination Status Address Low 1 (DSTATAR_LO1)
Destination Status Address High 1 (DSTATAR_HI1)
DMA Transfer Configuration Low 1 (CFG_LO1)
DMA Transfer Configuration High 1 (CFG_HI1)
Source Gather 1 (SGR1)
Destination Scatter 1 (DSR1)
Raw Interrupt Status (RawTfr)
Raw Status for Block Interrupts (RawBlock)
Raw Status for Source Transaction Interrupts (RawSrcTran)
Raw Status for Destination Transaction Interrupts (RawDstTran)
Raw Status for Error Interrupts (RawErr)
Status for Transfer Interrupts (StatusTfr)
Status for Block Interrupts (StatusBlock)
Status for Source Transaction Interrupts (StatusSrcTran)
Status for Destination Transaction Interrupts (StatusDstTran)
Status for Error Interrupts (StatusErr)
Mask for Transfer Interrupts (MaskTfr)
Mask for Block Interrupts (MaskBlock)
Mask for Source Transaction Interrupts (MaskSrcTran)
Mask for Destination Transaction Interrupts (MaskDstTran)
Mask for Error Interrupts (MaskErr)
Clear for Transfer Interrupts (ClearTfr)
Clear for Block Interrupts (ClearBlock)
Clear for Source Transaction Interrupts (ClearSrcTran)
Clear for Destination Transaction Interrupts (ClearDstTran)
Clear for Error Interrupts (ClearErr)
Combined Status (StatusInt)
DMA Configuration (DmaCfgReg)
DMA Channel Enable (ChEnReg)
Global DMA Configuration (GLOBAL_CFG)
I2C MMIO
I2C MMIO I2C Control (IC_CON) I2C Target Address (IC_TAR) I2C High Speed Master Mode Code Address (IC_HS_MADDR) Rx/Tx Data Buffer and Command (IC_DATA_CMD) Standard Speed I2C Clock SCL High Count (IC_SS_SCL_HCNT) Standard Speed I2C Clock SCL Low Count (IC_SS_SCL_LCNT) Fast Speed I2C Clock SCL High Count (IC_FS_SCL_HCNT) Fast Speed I2C Clock SCL Low Count (IC_FS_SCL_LCNT) High Speed I2C Clock SCL High Count (IC_HS_SCL_HCNT) High Speed I2C Clock SCL Low Count (IC_HS_SCL_LCNT) Interrupt Status (IC_INTR_STAT) Interrupt Mask (IC_INTR_MASK) Raw Interrupt Status (IC_RAW_INTR_STAT) Receive FIFO Threshold (IC_RX_TL) Transmit FIFO Threshold (IC_TX_TL) Clear Combined and Individual Interrupt (IC_CLR_INTR) Clear RX_UNDER Interrupt (IC_CLR_RX_UNDER) Clear RX_OVER Interrupt (IC_CLR_RX_OVER) Clear TX_OVER Interrupt (IC_CLR_TX_OVER) Clear RD_REQ Interrupt (IC_CLR_RD_REQ) Clear TX_ABRT Interrupt (IC_CLR_TX_ABRT) Clear RX_DONE Interrupt (IC_CLR_RX_DONE) Clear ACTIVITY Interrupt (IC_CLR_ACTIVITY) Clear STOP_DET Interrupt (IC_CLR_STOP_DET) Clear START_DET Interrupt (IC_CLR_START_DET) Clear GEN_CALL Interrupt (IC_CLR_GEN_CALL) I2C Enable (IC_ENABLE) I2C Status (IC_STATUS) Transmit FIFO Level (IC_TXFLR) Receive FIFO Level (IC_RXFLR) SDA Hold Time Length (IC_SDA_HOLD) Transmit Abort Source (IC_TX_ABRT_SOURCE) DMA Control (IC_DMA_CR) DMA Transmit Data Level (IC_DMA_TDLR) Receive Data Level (IC_DMA_RDLR) SDA Setup (IC_SDA_SETUP) ACK General Call (IC_ACK_GENERAL_CALL) I2C Enable Status (IC_ENABLE_STATUS) SS and FS Spike Suppression Limit (IC_FS_SPKLEN) HS Spike Suppression Limit (IC_HS_SPKLEN)
I2C Control (IC_CON)
I2C Target Address (IC_TAR)
I2C High Speed Master Mode Code Address (IC_HS_MADDR)
Rx/Tx Data Buffer and Command (IC_DATA_CMD)
Standard Speed I2C Clock SCL High Count (IC_SS_SCL_HCNT)
Standard Speed I2C Clock SCL Low Count (IC_SS_SCL_LCNT)
Fast Speed I2C Clock SCL High Count (IC_FS_SCL_HCNT)
Fast Speed I2C Clock SCL Low Count (IC_FS_SCL_LCNT)
High Speed I2C Clock SCL High Count (IC_HS_SCL_HCNT)
High Speed I2C Clock SCL Low Count (IC_HS_SCL_LCNT)
Interrupt Status (IC_INTR_STAT)
Interrupt Mask (IC_INTR_MASK)
Raw Interrupt Status (IC_RAW_INTR_STAT)
Receive FIFO Threshold (IC_RX_TL)
Transmit FIFO Threshold (IC_TX_TL)
Clear Combined and Individual Interrupt (IC_CLR_INTR)
Clear RX_UNDER Interrupt (IC_CLR_RX_UNDER)
Clear RX_OVER Interrupt (IC_CLR_RX_OVER)
Clear TX_OVER Interrupt (IC_CLR_TX_OVER)
Clear RD_REQ Interrupt (IC_CLR_RD_REQ)
Clear TX_ABRT Interrupt (IC_CLR_TX_ABRT)
Clear RX_DONE Interrupt (IC_CLR_RX_DONE)
Clear ACTIVITY Interrupt (IC_CLR_ACTIVITY)
Clear STOP_DET Interrupt (IC_CLR_STOP_DET)
Clear START_DET Interrupt (IC_CLR_START_DET)
Clear GEN_CALL Interrupt (IC_CLR_GEN_CALL)
I2C Enable (IC_ENABLE)
I2C Status (IC_STATUS)
Transmit FIFO Level (IC_TXFLR)
Receive FIFO Level (IC_RXFLR)
SDA Hold Time Length (IC_SDA_HOLD)
Transmit Abort Source (IC_TX_ABRT_SOURCE)
DMA Control (IC_DMA_CR)
DMA Transmit Data Level (IC_DMA_TDLR)
Receive Data Level (IC_DMA_RDLR)
SDA Setup (IC_SDA_SETUP)
ACK General Call (IC_ACK_GENERAL_CALL)
I2C Enable Status (IC_ENABLE_STATUS)
SS and FS Spike Suppression Limit (IC_FS_SPKLEN)
HS Spike Suppression Limit (IC_HS_SPKLEN)
I3C / I2C / UART / GSPI PCR
I3C / I2C / UART / GSPI PCR PCI Configuration Control for I2C0 (PCICFGCTR1) PCI Configuration Control for I2C1 (PCICFGCTR2) PCI Configuration Control for I2C2 (PCICFGCTR3) PCI Configuration Control for I2C3 (PCICFGCTR4) PCI Configuration Control for I2C4 (PCICFGCTR5) PCI Configuration Control for I2C5 (PCICFGCTR6) PCI Configuration Control for UART0 (PCICFGCTR7) PCI Configuration Control for UART1 (PCICFGCTR8) PCI Configuration Control for UART2 (PCICFGCTR9) PCI Configuration Control for UART3 (PCICFGCTR10) PCI Configuration Control for GSPI0 (PCICFGCTR11) PCI Configuration Control for GSPI1 (PCICFGCTR12) PCI Configuration Control for GSPI2 (PCICFGCTR13) PCI Configuration Control for GSPI3 (PCICFGCTR14) PCI Configuration Control for I3C (PCICFGCTR15)
PCI Configuration Control for I2C0 (PCICFGCTR1)
PCI Configuration Control for I2C1 (PCICFGCTR2)
PCI Configuration Control for I2C2 (PCICFGCTR3)
PCI Configuration Control for I2C3 (PCICFGCTR4)
PCI Configuration Control for I2C4 (PCICFGCTR5)
PCI Configuration Control for I2C5 (PCICFGCTR6)
PCI Configuration Control for UART0 (PCICFGCTR7)
PCI Configuration Control for UART1 (PCICFGCTR8)
PCI Configuration Control for UART2 (PCICFGCTR9)
PCI Configuration Control for UART3 (PCICFGCTR10)
PCI Configuration Control for GSPI0 (PCICFGCTR11)
PCI Configuration Control for GSPI1 (PCICFGCTR12)
PCI Configuration Control for GSPI2 (PCICFGCTR13)
PCI Configuration Control for GSPI3 (PCICFGCTR14)
PCI Configuration Control for I3C (PCICFGCTR15)
I3C Additional MMIO
I3C Additional MMIO REG MULT_BUS_INST_EXT_CAP (MULT_BUS_INST_EXT_CAP) REG MULT_BUS_INST_CNT (MULT_BUS_INST_CNT) REG MULT_BUS_INST_OFFSET (MULT_BUS_INST_OFFSET) REG VND_SPEC_EXT_CAP_2 (VND_SPEC_EXT_CAP_2) REG RESETS (RESETS) REG GENERAL (GENERAL) REG ACTIVELTR (ACTIVELTR) REG IDLELTR (IDLELTR) REG SW_SCRATCH_0 (SW_SCRATCH_0) REG CLOCK_GATE (CLOCK_GATE) REG DEVIDLE_CONTROL (DEVIDLE_CONTROL) REG HCI_COMP_VER_OVRD (HCI_COMP_VER_OVRD) REG I3C_Threshold (I3C_Threshold) REG Ext_CAP_End (Ext_CAP_End)
REG MULT_BUS_INST_EXT_CAP (MULT_BUS_INST_EXT_CAP)
REG MULT_BUS_INST_CNT (MULT_BUS_INST_CNT)
REG MULT_BUS_INST_OFFSET (MULT_BUS_INST_OFFSET)
REG VND_SPEC_EXT_CAP_2 (VND_SPEC_EXT_CAP_2)
REG RESETS (RESETS)
REG GENERAL (GENERAL)
REG ACTIVELTR (ACTIVELTR)
REG IDLELTR (IDLELTR)
REG SW_SCRATCH_0 (SW_SCRATCH_0)
REG CLOCK_GATE (CLOCK_GATE)
REG DEVIDLE_CONTROL (DEVIDLE_CONTROL)
REG HCI_COMP_VER_OVRD (HCI_COMP_VER_OVRD)
REG I3C_Threshold (I3C_Threshold)
REG Ext_CAP_End (Ext_CAP_End)
I3C DMA
I3C DMA REG CR_SETUP_0 (CR_SETUP_0) REG IBI_SETUP_0 (IBI_SETUP_0) REG CHUNK_CONTROL_0 (CHUNK_CONTROL_0) REG RH_INTR_STATUS_0 (RH_INTR_STATUS_0) REG RH_INTR_STATUS_ENABLE_0 (RH_INTR_STATUS_ENABLE_0) REG RH_INTR_SIGNAL_ENABLE_0 (RH_INTR_SIGNAL_ENABLE_0) REG RH_INTR_FORCE_0 (RH_INTR_FORCE_0) REG RH_STATUS_0 (RH_STATUS_0) REG RH_CONTROL_0 (RH_CONTROL_0) REG RH_OPERATION1_0 (RH_OPERATION1_0) REG RH_OPERATION2_0 (RH_OPERATION2_0) REG RH_CMD_RING_BASE_LO_0 (RH_CMD_RING_BASE_LO_0) REG RH_CMD_RING_BASE_HI_0 (RH_CMD_RING_BASE_HI_0) REG RH_RESP_RING_BASE_LO_0 (RH_RESP_RING_BASE_LO_0) REG RH_RESP_RING_BASE_HI_0 (RH_RESP_RING_BASE_HI_0) REG RH_IBI_STATUS_RING_BASE_LO_0 (RH_IBI_STATUS_RING_BASE_LO_0) REG RH_IBI_STATUS_RING_BASE_HI_0 (RH_IBI_STATUS_RING_BASE_HI_0) REG RH_IBI_DATA_RING_BASE_LO_0 (RH_IBI_DATA_RING_BASE_LO_0) REG RH_IBI_DATA_RING_BASE_HI_0 (RH_IBI_DATA_RING_BASE_HI_0) REG RHS_CONTROL_0 (RHS_CONTROL_0) REG RH0_OFFSET_0 (RH0_OFFSET_0) REG RH1_OFFSET_0 (RH1_OFFSET_0) REG RH2_OFFSET_0 (RH2_OFFSET_0) REG RH3_OFFSET_0 (RH3_OFFSET_0) REG RH4_OFFSET_0 (RH4_OFFSET_0) REG RH5_OFFSET_0 (RH5_OFFSET_0) REG RH6_OFFSET_0 (RH6_OFFSET_0) REG RH7_OFFSET_0 (RH7_OFFSET_0) REG CR_SETUP_2 (CR_SETUP_2) REG IBI_SETUP_2 (IBI_SETUP_2) REG CHUNK_CONTROL_2 (CHUNK_CONTROL_2) REG RH_INTR_STATUS_2 (RH_INTR_STATUS_2) REG RH_INTR_STATUS_ENABLE_2 (RH_INTR_STATUS_ENABLE_2) REG RH_INTR_SIGNAL_ENABLE_2 (RH_INTR_SIGNAL_ENABLE_2) REG RH_INTR_FORCE_2 (RH_INTR_FORCE_2) REG RH_STATUS_2 (RH_STATUS_2) REG RH_CONTROL_2 (RH_CONTROL_2) REG RH_OPERATION1_2 (RH_OPERATION1_2) REG RH_OPERATION2_2 (RH_OPERATION2_2) REG RH_CMD_RING_BASE_LO_2 (RH_CMD_RING_BASE_LO_2) REG RH_CMD_RING_BASE_HI_2 (RH_CMD_RING_BASE_HI_2) REG RH_RESP_RING_BASE_LO_2 (RH_RESP_RING_BASE_LO_2) REG RH_RESP_RING_BASE_HI_2 (RH_RESP_RING_BASE_HI_2) REG RH_IBI_STATUS_RING_BASE_LO_2 (RH_IBI_STATUS_RING_BASE_LO_2) REG RH_IBI_STATUS_RING_BASE_HI_2 (RH_IBI_STATUS_RING_BASE_HI_2) REG RH_IBI_DATA_RING_BASE_LO_2 (RH_IBI_DATA_RING_BASE_LO_2) REG RH_IBI_DATA_RING_BASE_HI_2 (RH_IBI_DATA_RING_BASE_HI_2) REG RHS_CONTROL_1 (RHS_CONTROL_1) REG RH0_OFFSET_1 (RH0_OFFSET_1) REG RH1_OFFSET_1 (RH1_OFFSET_1) REG RH2_OFFSET_1 (RH2_OFFSET_1) REG RH3_OFFSET_1 (RH3_OFFSET_1) REG RH4_OFFSET_1 (RH4_OFFSET_1) REG RH5_OFFSET_1 (RH5_OFFSET_1) REG RH6_OFFSET_1 (RH6_OFFSET_1) REG RH7_OFFSET_1 (RH7_OFFSET_1) REG CR_SETUP_1 (CR_SETUP_1) REG IBI_SETUP_1 (IBI_SETUP_1) REG CHUNK_CONTROL_1 (CHUNK_CONTROL_1) REG RH_INTR_STATUS_1 (RH_INTR_STATUS_1) REG RH_INTR_STATUS_ENABLE_1 (RH_INTR_STATUS_ENABLE_1) REG RH_INTR_SIGNAL_ENABLE_1 (RH_INTR_SIGNAL_ENABLE_1) REG RH_INTR_FORCE_1 (RH_INTR_FORCE_1) REG RH_STATUS_1 (RH_STATUS_1) REG RH_CONTROL_1 (RH_CONTROL_1) REG RH_OPERATION1_1 (RH_OPERATION1_1) REG RH_OPERATION2_1 (RH_OPERATION2_1) REG RH_CMD_RING_BASE_LO_1 (RH_CMD_RING_BASE_LO_1) REG RH_CMD_RING_BASE_HI_1 (RH_CMD_RING_BASE_HI_1) REG RH_RESP_RING_BASE_LO_1 (RH_RESP_RING_BASE_LO_1) REG RH_RESP_RING_BASE_HI_1 (RH_RESP_RING_BASE_HI_1) REG RH_IBI_STATUS_RING_BASE_LO_1 (RH_IBI_STATUS_RING_BASE_LO_1) REG RH_IBI_STATUS_RING_BASE_HI_1 (RH_IBI_STATUS_RING_BASE_HI_1) REG RH_IBI_DATA_RING_BASE_LO_1 (RH_IBI_DATA_RING_BASE_LO_1) REG RH_IBI_DATA_RING_BASE_HI_1 (RH_IBI_DATA_RING_BASE_HI_1) REG CR_SETUP_3 (CR_SETUP_3) REG IBI_SETUP_3 (IBI_SETUP_3) REG CHUNK_CONTROL_3 (CHUNK_CONTROL_3) REG RH_INTR_STATUS_3 (RH_INTR_STATUS_3) REG RH_INTR_STATUS_ENABLE_3 (RH_INTR_STATUS_ENABLE_3) REG RH_INTR_SIGNAL_ENABLE_3 (RH_INTR_SIGNAL_ENABLE_3) REG RH_INTR_FORCE_3 (RH_INTR_FORCE_3) REG RH_STATUS_3 (RH_STATUS_3) REG RH_CONTROL_3 (RH_CONTROL_3) REG RH_OPERATION1_3 (RH_OPERATION1_3) REG RH_OPERATION2_3 (RH_OPERATION2_3) REG RH_CMD_RING_BASE_LO_3 (RH_CMD_RING_BASE_LO_3) REG RH_CMD_RING_BASE_HI_3 (RH_CMD_RING_BASE_HI_3) REG RH_RESP_RING_BASE_LO_3 (RH_RESP_RING_BASE_LO_3) REG RH_RESP_RING_BASE_HI_3 (RH_RESP_RING_BASE_HI_3) REG RH_IBI_STATUS_RING_BASE_LO_3 (RH_IBI_STATUS_RING_BASE_LO_3) REG RH_IBI_STATUS_RING_BASE_HI_3 (RH_IBI_STATUS_RING_BASE_HI_3) REG RH_IBI_DATA_RING_BASE_LO_3 (RH_IBI_DATA_RING_BASE_LO_3) REG RH_IBI_DATA_RING_BASE_HI_3 (RH_IBI_DATA_RING_BASE_HI_3)
REG CR_SETUP_0 (CR_SETUP_0)
REG IBI_SETUP_0 (IBI_SETUP_0)
REG CHUNK_CONTROL_0 (CHUNK_CONTROL_0)
REG RH_INTR_STATUS_0 (RH_INTR_STATUS_0)
REG RH_INTR_STATUS_ENABLE_0 (RH_INTR_STATUS_ENABLE_0)
REG RH_INTR_SIGNAL_ENABLE_0 (RH_INTR_SIGNAL_ENABLE_0)
REG RH_INTR_FORCE_0 (RH_INTR_FORCE_0)
REG RH_STATUS_0 (RH_STATUS_0)
REG RH_CONTROL_0 (RH_CONTROL_0)
REG RH_OPERATION1_0 (RH_OPERATION1_0)
REG RH_OPERATION2_0 (RH_OPERATION2_0)
REG RH_CMD_RING_BASE_LO_0 (RH_CMD_RING_BASE_LO_0)
REG RH_CMD_RING_BASE_HI_0 (RH_CMD_RING_BASE_HI_0)
REG RH_RESP_RING_BASE_LO_0 (RH_RESP_RING_BASE_LO_0)
REG RH_RESP_RING_BASE_HI_0 (RH_RESP_RING_BASE_HI_0)
REG RH_IBI_STATUS_RING_BASE_LO_0 (RH_IBI_STATUS_RING_BASE_LO_0)
REG RH_IBI_STATUS_RING_BASE_HI_0 (RH_IBI_STATUS_RING_BASE_HI_0)
REG RH_IBI_DATA_RING_BASE_LO_0 (RH_IBI_DATA_RING_BASE_LO_0)
REG RH_IBI_DATA_RING_BASE_HI_0 (RH_IBI_DATA_RING_BASE_HI_0)
REG RHS_CONTROL_0 (RHS_CONTROL_0)
REG RH0_OFFSET_0 (RH0_OFFSET_0)
REG RH1_OFFSET_0 (RH1_OFFSET_0)
REG RH2_OFFSET_0 (RH2_OFFSET_0)
REG RH3_OFFSET_0 (RH3_OFFSET_0)
REG RH4_OFFSET_0 (RH4_OFFSET_0)
REG RH5_OFFSET_0 (RH5_OFFSET_0)
REG RH6_OFFSET_0 (RH6_OFFSET_0)
REG RH7_OFFSET_0 (RH7_OFFSET_0)
REG CR_SETUP_2 (CR_SETUP_2)
REG IBI_SETUP_2 (IBI_SETUP_2)
REG CHUNK_CONTROL_2 (CHUNK_CONTROL_2)
REG RH_INTR_STATUS_2 (RH_INTR_STATUS_2)
REG RH_INTR_STATUS_ENABLE_2 (RH_INTR_STATUS_ENABLE_2)
REG RH_INTR_SIGNAL_ENABLE_2 (RH_INTR_SIGNAL_ENABLE_2)
REG RH_INTR_FORCE_2 (RH_INTR_FORCE_2)
REG RH_STATUS_2 (RH_STATUS_2)
REG RH_CONTROL_2 (RH_CONTROL_2)
REG RH_OPERATION1_2 (RH_OPERATION1_2)
REG RH_OPERATION2_2 (RH_OPERATION2_2)
REG RH_CMD_RING_BASE_LO_2 (RH_CMD_RING_BASE_LO_2)
REG RH_CMD_RING_BASE_HI_2 (RH_CMD_RING_BASE_HI_2)
REG RH_RESP_RING_BASE_LO_2 (RH_RESP_RING_BASE_LO_2)
REG RH_RESP_RING_BASE_HI_2 (RH_RESP_RING_BASE_HI_2)
REG RH_IBI_STATUS_RING_BASE_LO_2 (RH_IBI_STATUS_RING_BASE_LO_2)
REG RH_IBI_STATUS_RING_BASE_HI_2 (RH_IBI_STATUS_RING_BASE_HI_2)
REG RH_IBI_DATA_RING_BASE_LO_2 (RH_IBI_DATA_RING_BASE_LO_2)
REG RH_IBI_DATA_RING_BASE_HI_2 (RH_IBI_DATA_RING_BASE_HI_2)
REG RHS_CONTROL_1 (RHS_CONTROL_1)
REG RH0_OFFSET_1 (RH0_OFFSET_1)
REG RH1_OFFSET_1 (RH1_OFFSET_1)
REG RH2_OFFSET_1 (RH2_OFFSET_1)
REG RH3_OFFSET_1 (RH3_OFFSET_1)
REG RH4_OFFSET_1 (RH4_OFFSET_1)
REG RH5_OFFSET_1 (RH5_OFFSET_1)
REG RH6_OFFSET_1 (RH6_OFFSET_1)
REG RH7_OFFSET_1 (RH7_OFFSET_1)
REG CR_SETUP_1 (CR_SETUP_1)
REG IBI_SETUP_1 (IBI_SETUP_1)
REG CHUNK_CONTROL_1 (CHUNK_CONTROL_1)
REG RH_INTR_STATUS_1 (RH_INTR_STATUS_1)
REG RH_INTR_STATUS_ENABLE_1 (RH_INTR_STATUS_ENABLE_1)
REG RH_INTR_SIGNAL_ENABLE_1 (RH_INTR_SIGNAL_ENABLE_1)
REG RH_INTR_FORCE_1 (RH_INTR_FORCE_1)
REG RH_STATUS_1 (RH_STATUS_1)
REG RH_CONTROL_1 (RH_CONTROL_1)
REG RH_OPERATION1_1 (RH_OPERATION1_1)
REG RH_OPERATION2_1 (RH_OPERATION2_1)
REG RH_CMD_RING_BASE_LO_1 (RH_CMD_RING_BASE_LO_1)
REG RH_CMD_RING_BASE_HI_1 (RH_CMD_RING_BASE_HI_1)
REG RH_RESP_RING_BASE_LO_1 (RH_RESP_RING_BASE_LO_1)
REG RH_RESP_RING_BASE_HI_1 (RH_RESP_RING_BASE_HI_1)
REG RH_IBI_STATUS_RING_BASE_LO_1 (RH_IBI_STATUS_RING_BASE_LO_1)
REG RH_IBI_STATUS_RING_BASE_HI_1 (RH_IBI_STATUS_RING_BASE_HI_1)
REG RH_IBI_DATA_RING_BASE_LO_1 (RH_IBI_DATA_RING_BASE_LO_1)
REG RH_IBI_DATA_RING_BASE_HI_1 (RH_IBI_DATA_RING_BASE_HI_1)
REG CR_SETUP_3 (CR_SETUP_3)
REG IBI_SETUP_3 (IBI_SETUP_3)
REG CHUNK_CONTROL_3 (CHUNK_CONTROL_3)
REG RH_INTR_STATUS_3 (RH_INTR_STATUS_3)
REG RH_INTR_STATUS_ENABLE_3 (RH_INTR_STATUS_ENABLE_3)
REG RH_INTR_SIGNAL_ENABLE_3 (RH_INTR_SIGNAL_ENABLE_3)
REG RH_INTR_FORCE_3 (RH_INTR_FORCE_3)
REG RH_STATUS_3 (RH_STATUS_3)
REG RH_CONTROL_3 (RH_CONTROL_3)
REG RH_OPERATION1_3 (RH_OPERATION1_3)
REG RH_OPERATION2_3 (RH_OPERATION2_3)
REG RH_CMD_RING_BASE_LO_3 (RH_CMD_RING_BASE_LO_3)
REG RH_CMD_RING_BASE_HI_3 (RH_CMD_RING_BASE_HI_3)
REG RH_RESP_RING_BASE_LO_3 (RH_RESP_RING_BASE_LO_3)
REG RH_RESP_RING_BASE_HI_3 (RH_RESP_RING_BASE_HI_3)
REG RH_IBI_STATUS_RING_BASE_LO_3 (RH_IBI_STATUS_RING_BASE_LO_3)
REG RH_IBI_STATUS_RING_BASE_HI_3 (RH_IBI_STATUS_RING_BASE_HI_3)
REG RH_IBI_DATA_RING_BASE_LO_3 (RH_IBI_DATA_RING_BASE_LO_3)
REG RH_IBI_DATA_RING_BASE_HI_3 (RH_IBI_DATA_RING_BASE_HI_3)
I3C MMIO
I3C MMIO REG HCI_VERSION (HCI_VERSION) REG DEVICE_CONTROL (DEVICE_CONTROL) REG DEVICE_ADDR (DEVICE_ADDR) REG DEVICE_CAPABILITIES (DEVICE_CAPABILITIES) REG RESET_CTRL (RESET_CTRL) REG PRESENT_STATE (PRESENT_STATE) REG INTR_STATUS (INTR_STATUS) REG INTR_STATUS_ENABLE (INTR_STATUS_ENABLE) REG INTR_SIGNAL_ENABLE (INTR_SIGNAL_ENABLE) REG INTR_FORCE (INTR_FORCE) REG DAT_SECTION_OFFSET (DAT_SECTION_OFFSET) REG DCT_SECTION_OFFSET (DCT_SECTION_OFFSET) REG RING_HEADERS_SECTION_OFFSET (RING_HEADERS_SECTION_OFFSET) REG PIO_SECTION_OFFSET (PIO_SECTION_OFFSET) REG EXTCAPS_SECTION_OFFSET (EXTCAPS_SECTION_OFFSET) REG IBI_NOTIFY_CTRL (IBI_NOTIFY_CTRL) REG DEV_ADDR_TABLE1_LOC1 (DEV_ADDR_TABLE1_LOC1) REG DEV_ADDR_TABLE1_LOC2 (DEV_ADDR_TABLE1_LOC2) REG DEV_ADDR_TABLE2_LOC1 (DEV_ADDR_TABLE2_LOC1) REG DEV_ADDR_TABLE2_LOC2 (DEV_ADDR_TABLE2_LOC2) REG DEV_ADDR_TABLE3_LOC1 (DEV_ADDR_TABLE3_LOC1) REG DEV_ADDR_TABLE3_LOC2 (DEV_ADDR_TABLE3_LOC2) REG DEV_ADDR_TABLE4_LOC1 (DEV_ADDR_TABLE4_LOC1) REG DEV_ADDR_TABLE4_LOC2 (DEV_ADDR_TABLE4_LOC2) REG DEV_ADDR_TABLE5_LOC1 (DEV_ADDR_TABLE5_LOC1) REG DEV_ADDR_TABLE5_LOC2 (DEV_ADDR_TABLE5_LOC2) REG DEV_ADDR_TABLE6_LOC1 (DEV_ADDR_TABLE6_LOC1) REG DEV_ADDR_TABLE6_LOC2 (DEV_ADDR_TABLE6_LOC2) REG DEV_ADDR_TABLE7_LOC1 (DEV_ADDR_TABLE7_LOC1) REG DEV_ADDR_TABLE7_LOC2 (DEV_ADDR_TABLE7_LOC2) REG DEV_ADDR_TABLE8_LOC1 (DEV_ADDR_TABLE8_LOC1) REG DEV_ADDR_TABLE8_LOC2 (DEV_ADDR_TABLE8_LOC2) REG COMMAND_QUEUE_PORT (COMMAND_QUEUE_PORT) REG RESPONSE_QUEUE_PORT (RESPONSE_QUEUE_PORT) REG DATA_PORT (DATA_PORT) REG IBI_PORT (IBI_PORT) REG QUEUE_THLD_CTRL (QUEUE_THLD_CTRL) REG DATA_BUFFER_THLD_CTRL (DATA_BUFFER_THLD_CTRL) REG QUEUE_SIZE_CTRL (QUEUE_SIZE_CTRL) REG DEV_CHAR_TABLE1_LOC1 (DEV_CHAR_TABLE1_LOC1) REG DEV_CHAR_TABLE1_LOC2 (DEV_CHAR_TABLE1_LOC2) REG DEV_CHAR_TABLE1_LOC3 (DEV_CHAR_TABLE1_LOC3) REG DEV_CHAR_TABLE1_LOC4 (DEV_CHAR_TABLE1_LOC4) REG DEV_CHAR_TABLE2_LOC1 (DEV_CHAR_TABLE2_LOC1) REG DEV_CHAR_TABLE2_LOC2 (DEV_CHAR_TABLE2_LOC2) REG DEV_CHAR_TABLE2_LOC3 (DEV_CHAR_TABLE2_LOC3) REG DEV_CHAR_TABLE2_LOC4 (DEV_CHAR_TABLE2_LOC4) REG DEV_CHAR_TABLE3_LOC1 (DEV_CHAR_TABLE3_LOC1) REG DEV_CHAR_TABLE3_LOC2 (DEV_CHAR_TABLE3_LOC2) REG DEV_CHAR_TABLE3_LOC3 (DEV_CHAR_TABLE3_LOC3) REG DEV_CHAR_TABLE3_LOC4 (DEV_CHAR_TABLE3_LOC4) REG DEV_CHAR_TABLE4_LOC1 (DEV_CHAR_TABLE4_LOC1) REG DEV_CHAR_TABLE4_LOC2 (DEV_CHAR_TABLE4_LOC2) REG DEV_CHAR_TABLE4_LOC3 (DEV_CHAR_TABLE4_LOC3) REG DEV_CHAR_TABLE4_LOC4 (DEV_CHAR_TABLE4_LOC4) REG DEV_CHAR_TABLE5_LOC1 (DEV_CHAR_TABLE5_LOC1) REG DEV_CHAR_TABLE5_LOC2 (DEV_CHAR_TABLE5_LOC2) REG DEV_CHAR_TABLE5_LOC3 (DEV_CHAR_TABLE5_LOC3) REG DEV_CHAR_TABLE5_LOC4 (DEV_CHAR_TABLE5_LOC4) REG DEV_CHAR_TABLE6_LOC1 (DEV_CHAR_TABLE6_LOC1) REG DEV_CHAR_TABLE6_LOC2 (DEV_CHAR_TABLE6_LOC2) REG DEV_CHAR_TABLE6_LOC3 (DEV_CHAR_TABLE6_LOC3) REG DEV_CHAR_TABLE6_LOC4 (DEV_CHAR_TABLE6_LOC4) REG DEV_CHAR_TABLE7_LOC1 (DEV_CHAR_TABLE7_LOC1) REG DEV_CHAR_TABLE7_LOC2 (DEV_CHAR_TABLE7_LOC2) REG DEV_CHAR_TABLE7_LOC3 (DEV_CHAR_TABLE7_LOC3) REG DEV_CHAR_TABLE7_LOC4 (DEV_CHAR_TABLE7_LOC4) REG DEV_CHAR_TABLE8_LOC1 (DEV_CHAR_TABLE8_LOC1) REG DEV_CHAR_TABLE8_LOC2 (DEV_CHAR_TABLE8_LOC2) REG DEV_CHAR_TABLE8_LOC3 (DEV_CHAR_TABLE8_LOC3) REG DEV_CHAR_TABLE8_LOC4 (DEV_CHAR_TABLE8_LOC4) REG HW_IDENTIFICATION_HEADER (HW_IDENTIFICATION_HEADER) REG COMP_MANUFACTURER (COMP_MANUFACTURER) REG COMP_VERSION (COMP_VERSION) REG COMP_TYPE (COMP_TYPE) REG BUS_TIMING_HEADER (BUS_TIMING_HEADER) REG SCL_I3C_OD_TIMING (SCL_I3C_OD_TIMING) REG SCL_I3C_PP_TIMING (SCL_I3C_PP_TIMING) REG SCL_I2C_FM_TIMING (SCL_I2C_FM_TIMING) REG SCL_I2C_FMP_TIMING (SCL_I2C_FMP_TIMING) REG SCL_I2C_SS_TIMING (SCL_I2C_SS_TIMING) REG SCL_EXT_LCNT_TIMING (SCL_EXT_LCNT_TIMING) REG SCL_EXT_TERMN_LCNT_TIMING (SCL_EXT_TERMN_LCNT_TIMING) REG SDA_HOLD_SWITCH_DLY_TIMING (SDA_HOLD_SWITCH_DLY_TIMING) REG BUS_FREE_TIMING (BUS_FREE_TIMING) REG DS_EXTCAP_HEADER (DS_EXTCAP_HEADER) REG QUEUE_STATUS_LEVEL (QUEUE_STATUS_LEVEL) REG DATA_BUFFER_STATUS_LEVEL (DATA_BUFFER_STATUS_LEVEL) REG PRESENT_STATE_DEBUG (PRESENT_STATE_DEBUG) REG MASTER_EXT_HEADER (MASTER_EXT_HEADER) REG MASTER_CONFIG (MASTER_CONFIG)
REG HCI_VERSION (HCI_VERSION)
REG DEVICE_CONTROL (DEVICE_CONTROL)
REG DEVICE_ADDR (DEVICE_ADDR)
REG DEVICE_CAPABILITIES (DEVICE_CAPABILITIES)
REG RESET_CTRL (RESET_CTRL)
REG PRESENT_STATE (PRESENT_STATE)
REG INTR_STATUS (INTR_STATUS)
REG INTR_STATUS_ENABLE (INTR_STATUS_ENABLE)
REG INTR_SIGNAL_ENABLE (INTR_SIGNAL_ENABLE)
REG INTR_FORCE (INTR_FORCE)
REG DAT_SECTION_OFFSET (DAT_SECTION_OFFSET)
REG DCT_SECTION_OFFSET (DCT_SECTION_OFFSET)
REG RING_HEADERS_SECTION_OFFSET (RING_HEADERS_SECTION_OFFSET)
REG PIO_SECTION_OFFSET (PIO_SECTION_OFFSET)
REG EXTCAPS_SECTION_OFFSET (EXTCAPS_SECTION_OFFSET)
REG IBI_NOTIFY_CTRL (IBI_NOTIFY_CTRL)
REG DEV_ADDR_TABLE1_LOC1 (DEV_ADDR_TABLE1_LOC1)
REG DEV_ADDR_TABLE1_LOC2 (DEV_ADDR_TABLE1_LOC2)
REG DEV_ADDR_TABLE2_LOC1 (DEV_ADDR_TABLE2_LOC1)
REG DEV_ADDR_TABLE2_LOC2 (DEV_ADDR_TABLE2_LOC2)
REG DEV_ADDR_TABLE3_LOC1 (DEV_ADDR_TABLE3_LOC1)
REG DEV_ADDR_TABLE3_LOC2 (DEV_ADDR_TABLE3_LOC2)
REG DEV_ADDR_TABLE4_LOC1 (DEV_ADDR_TABLE4_LOC1)
REG DEV_ADDR_TABLE4_LOC2 (DEV_ADDR_TABLE4_LOC2)
REG DEV_ADDR_TABLE5_LOC1 (DEV_ADDR_TABLE5_LOC1)
REG DEV_ADDR_TABLE5_LOC2 (DEV_ADDR_TABLE5_LOC2)
REG DEV_ADDR_TABLE6_LOC1 (DEV_ADDR_TABLE6_LOC1)
REG DEV_ADDR_TABLE6_LOC2 (DEV_ADDR_TABLE6_LOC2)
REG DEV_ADDR_TABLE7_LOC1 (DEV_ADDR_TABLE7_LOC1)
REG DEV_ADDR_TABLE7_LOC2 (DEV_ADDR_TABLE7_LOC2)
REG DEV_ADDR_TABLE8_LOC1 (DEV_ADDR_TABLE8_LOC1)
REG DEV_ADDR_TABLE8_LOC2 (DEV_ADDR_TABLE8_LOC2)
REG COMMAND_QUEUE_PORT (COMMAND_QUEUE_PORT)
REG RESPONSE_QUEUE_PORT (RESPONSE_QUEUE_PORT)
REG DATA_PORT (DATA_PORT)
REG IBI_PORT (IBI_PORT)
REG QUEUE_THLD_CTRL (QUEUE_THLD_CTRL)
REG DATA_BUFFER_THLD_CTRL (DATA_BUFFER_THLD_CTRL)
REG QUEUE_SIZE_CTRL (QUEUE_SIZE_CTRL)
REG DEV_CHAR_TABLE1_LOC1 (DEV_CHAR_TABLE1_LOC1)
REG DEV_CHAR_TABLE1_LOC2 (DEV_CHAR_TABLE1_LOC2)
REG DEV_CHAR_TABLE1_LOC3 (DEV_CHAR_TABLE1_LOC3)
REG DEV_CHAR_TABLE1_LOC4 (DEV_CHAR_TABLE1_LOC4)
REG DEV_CHAR_TABLE2_LOC1 (DEV_CHAR_TABLE2_LOC1)
REG DEV_CHAR_TABLE2_LOC2 (DEV_CHAR_TABLE2_LOC2)
REG DEV_CHAR_TABLE2_LOC3 (DEV_CHAR_TABLE2_LOC3)
REG DEV_CHAR_TABLE2_LOC4 (DEV_CHAR_TABLE2_LOC4)
REG DEV_CHAR_TABLE3_LOC1 (DEV_CHAR_TABLE3_LOC1)
REG DEV_CHAR_TABLE3_LOC2 (DEV_CHAR_TABLE3_LOC2)
REG DEV_CHAR_TABLE3_LOC3 (DEV_CHAR_TABLE3_LOC3)
REG DEV_CHAR_TABLE3_LOC4 (DEV_CHAR_TABLE3_LOC4)
REG DEV_CHAR_TABLE4_LOC1 (DEV_CHAR_TABLE4_LOC1)
REG DEV_CHAR_TABLE4_LOC2 (DEV_CHAR_TABLE4_LOC2)
REG DEV_CHAR_TABLE4_LOC3 (DEV_CHAR_TABLE4_LOC3)
REG DEV_CHAR_TABLE4_LOC4 (DEV_CHAR_TABLE4_LOC4)
REG DEV_CHAR_TABLE5_LOC1 (DEV_CHAR_TABLE5_LOC1)
REG DEV_CHAR_TABLE5_LOC2 (DEV_CHAR_TABLE5_LOC2)
REG DEV_CHAR_TABLE5_LOC3 (DEV_CHAR_TABLE5_LOC3)
REG DEV_CHAR_TABLE5_LOC4 (DEV_CHAR_TABLE5_LOC4)
REG DEV_CHAR_TABLE6_LOC1 (DEV_CHAR_TABLE6_LOC1)
REG DEV_CHAR_TABLE6_LOC2 (DEV_CHAR_TABLE6_LOC2)
REG DEV_CHAR_TABLE6_LOC3 (DEV_CHAR_TABLE6_LOC3)
REG DEV_CHAR_TABLE6_LOC4 (DEV_CHAR_TABLE6_LOC4)
REG DEV_CHAR_TABLE7_LOC1 (DEV_CHAR_TABLE7_LOC1)
REG DEV_CHAR_TABLE7_LOC2 (DEV_CHAR_TABLE7_LOC2)
REG DEV_CHAR_TABLE7_LOC3 (DEV_CHAR_TABLE7_LOC3)
REG DEV_CHAR_TABLE7_LOC4 (DEV_CHAR_TABLE7_LOC4)
REG DEV_CHAR_TABLE8_LOC1 (DEV_CHAR_TABLE8_LOC1)
REG DEV_CHAR_TABLE8_LOC2 (DEV_CHAR_TABLE8_LOC2)
REG DEV_CHAR_TABLE8_LOC3 (DEV_CHAR_TABLE8_LOC3)
REG DEV_CHAR_TABLE8_LOC4 (DEV_CHAR_TABLE8_LOC4)
REG HW_IDENTIFICATION_HEADER (HW_IDENTIFICATION_HEADER)
REG COMP_MANUFACTURER (COMP_MANUFACTURER)
REG COMP_VERSION (COMP_VERSION)
REG COMP_TYPE (COMP_TYPE)
REG BUS_TIMING_HEADER (BUS_TIMING_HEADER)
REG SCL_I3C_OD_TIMING (SCL_I3C_OD_TIMING)
REG SCL_I3C_PP_TIMING (SCL_I3C_PP_TIMING)
REG SCL_I2C_FM_TIMING (SCL_I2C_FM_TIMING)
REG SCL_I2C_FMP_TIMING (SCL_I2C_FMP_TIMING)
REG SCL_I2C_SS_TIMING (SCL_I2C_SS_TIMING)
REG SCL_EXT_LCNT_TIMING (SCL_EXT_LCNT_TIMING)
REG SCL_EXT_TERMN_LCNT_TIMING (SCL_EXT_TERMN_LCNT_TIMING)
REG SDA_HOLD_SWITCH_DLY_TIMING (SDA_HOLD_SWITCH_DLY_TIMING)
REG BUS_FREE_TIMING (BUS_FREE_TIMING)
REG DS_EXTCAP_HEADER (DS_EXTCAP_HEADER)
REG QUEUE_STATUS_LEVEL (QUEUE_STATUS_LEVEL)
REG DATA_BUFFER_STATUS_LEVEL (DATA_BUFFER_STATUS_LEVEL)
REG PRESENT_STATE_DEBUG (PRESENT_STATE_DEBUG)
REG MASTER_EXT_HEADER (MASTER_EXT_HEADER)
REG MASTER_CONFIG (MASTER_CONFIG)
I3C PCI Configuration
I3C PCI Configuration Device Id And Vendor Id Register (DEVVENDID) Status And Command (STATUSCOMMAND) Revision Id And Class Code (REVCLASSCODE) Cache Line Latency Header And Bist (CLLATHEADERBIST) Base Address Register (BAR) Base Address Register High (BAR_HIGH) Base Address Register1 (BAR1) Base Address Register1 High (BAR1_HIGH) Subsystem Vendor And Subsystem Id (SUBSYSTEMID) Expansion Rom Base Address (EXPANSION_ROM_BASEADDR) Capabilities Pointer Register (CAPABILITYPTR) Interrupt Register (INTERRUPTREG) Power Management Capability Id (POWERCAPID) Power Management Control And Status Register (PMECTRLSTATUS) Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD) Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG) Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG) Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG) D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG) General Purpose Read Write Register1 (GEN_REGRW1) General Purpose Read Write Register2 (GEN_REGRW2) General Purpose Read Write Register3 (GEN_REGRW3) General Purpose Read Write Register4 (GEN_REGRW4) General Purpose Input Register (GEN_INPUT_REG)
Device Id And Vendor Id Register (DEVVENDID)
Status And Command (STATUSCOMMAND)
Revision Id And Class Code (REVCLASSCODE)
Cache Line Latency Header And Bist (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Subsystem Vendor And Subsystem Id (SUBSYSTEMID)
Expansion Rom Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer Register (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Capability Id (POWERCAPID)
Power Management Control And Status Register (PMECTRLSTATUS)
Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD)
Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG)
Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG)
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write Register1 (GEN_REGRW1)
General Purpose Read Write Register2 (GEN_REGRW2)
General Purpose Read Write Register3 (GEN_REGRW3)
General Purpose Read Write Register4 (GEN_REGRW4)
General Purpose Input Register (GEN_INPUT_REG)
IDE-Redirect (IDE-R) PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration Device ID And Vendor ID (IDE_HOST_DID_VID) Status And Command (IDE_HOST_STS_CMD) Class Code And Revision ID (IDE_HOST_CC_RID) BIST, Header Type, Latency Timer, And Cache Line Size (IDE_HOST_BIST_HTYPE_LT_CLS) IDE Primary Command Block IO BAR (IDE_HOST_PCMDIOBAR) IDE Primary Control Block IO BAR (IDE_HOST_PCTLIOBAR) IDE Secondary Command Block IO BAR (IDE_HOST_SCMDIOBAR) IDE Secondary Control Block IO BAR (IDE_HOST_SCTLIOBAR) IDE Bus Master Block IO BAR (IDE_HOST_BMIOBAR) Cardbus CIS Pointer (IDE_HOST_CCP) Subsystem ID And Subsystem Vendor ID (IDE_HOST_SID_SVID) Expansion ROM Base Address (IDE_HOST_XRBAR) Capabilities List Pointer (IDE_HOST_CAPP) Maximum Latency, Minimum Grant, Interrupt Pin And Interrupt Line (IDE_HOST_MAXL_MING_INTP_INTL) MSI Message Control, Next Pointer And Capability ID (IDE_HOST_MSIMC_MSINP_MSICID) MSI Message Address (IDE_HOST_MSIMA) MSI Message Upper Address (IDE_HOST_MSIMUA) MSI Message Data (IDE_HOST_MSIMD) Power Management Capabilities, Next Pointer And Capability ID (IDE_HOST_PMCAP_PMNP_PMCID) Power Management Data, Control/Status Register Bridge Support Extensions, Control And Status (IDE_HOST_PMD_PMCSRBSE_PMCSR)
Device ID And Vendor ID (IDE_HOST_DID_VID)
Status And Command (IDE_HOST_STS_CMD)
Class Code And Revision ID (IDE_HOST_CC_RID)
BIST, Header Type, Latency Timer, And Cache Line Size (IDE_HOST_BIST_HTYPE_LT_CLS)
IDE Primary Command Block IO BAR (IDE_HOST_PCMDIOBAR)
IDE Primary Control Block IO BAR (IDE_HOST_PCTLIOBAR)
IDE Secondary Command Block IO BAR (IDE_HOST_SCMDIOBAR)
IDE Secondary Control Block IO BAR (IDE_HOST_SCTLIOBAR)
IDE Bus Master Block IO BAR (IDE_HOST_BMIOBAR)
Cardbus CIS Pointer (IDE_HOST_CCP)
Subsystem ID And Subsystem Vendor ID (IDE_HOST_SID_SVID)
Expansion ROM Base Address (IDE_HOST_XRBAR)
Capabilities List Pointer (IDE_HOST_CAPP)
Maximum Latency, Minimum Grant, Interrupt Pin And Interrupt Line (IDE_HOST_MAXL_MING_INTP_INTL)
MSI Message Control, Next Pointer And Capability ID (IDE_HOST_MSIMC_MSINP_MSICID)
MSI Message Address (IDE_HOST_MSIMA)
MSI Message Upper Address (IDE_HOST_MSIMUA)
MSI Message Data (IDE_HOST_MSIMD)
Power Management Capabilities, Next Pointer And Capability ID (IDE_HOST_PMCAP_PMNP_PMCID)
Power Management Data, Control/Status Register Bridge Support Extensions, Control And Status (IDE_HOST_PMD_PMCSRBSE_PMCSR)
Integrated GbE PCI Configuration
Integrated GbE PCI Configuration GbE Vendor and Device Identification Register (DMI_CONFIG0) PCI Command & Status Register (DMI_CONFIG1) Revision Identification & Class Code Register (DMI_CONFIG2) Cache Line Size Primary Latency Timer & Header Type Register (DMI_CONFIG3) Memory Base Address Register A (DMI_CONFIG4) Subsystem Vendor & Subsytem ID (DMI_CONFIG11) Expansion ROM Base Address Register (DMI_CONFIG12) Capabilities List Pointer Register (DMI_CONFIG13) Interrupt Information & Maximum Latency/Minimum GrantRegister (DMI_CONFIG15) LAN Disable Control (LANDISCTRL) Lock LAN Disable (LOCKLANDIS) System Time Control High Register (LTRC) Capabilities List and Power Managment Capabilities Register (PM0) PCI Power Management Control Status & Data Register (PM1) Capabilities List 2 & Message Control Register (DMI_MS0) Message Address Low Register (DMI_MS1) Message Address High Register (DMI_MS2) Message Data Register (DMI_MS3)
GbE Vendor and Device Identification Register (DMI_CONFIG0)
PCI Command & Status Register (DMI_CONFIG1)
Revision Identification & Class Code Register (DMI_CONFIG2)
Cache Line Size Primary Latency Timer & Header Type Register (DMI_CONFIG3)
Memory Base Address Register A (DMI_CONFIG4)
Subsystem Vendor & Subsytem ID (DMI_CONFIG11)
Expansion ROM Base Address Register (DMI_CONFIG12)
Capabilities List Pointer Register (DMI_CONFIG13)
Interrupt Information & Maximum Latency/Minimum GrantRegister (DMI_CONFIG15)
LAN Disable Control (LANDISCTRL)
Lock LAN Disable (LOCKLANDIS)
System Time Control High Register (LTRC)
Capabilities List and Power Managment Capabilities Register (PM0)
PCI Power Management Control Status & Data Register (PM1)
Capabilities List 2 & Message Control Register (DMI_MS0)
Message Address Low Register (DMI_MS1)
Message Address High Register (DMI_MS2)
Message Data Register (DMI_MS3)
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) MMIO HOST Firmware Status (ISH_HOST_FWSTS_HOST) HOST Communication (HOST_COMM_HOST) Inbound DoorbellHOST To ISH (HOST2ISH_DOORBELL_HOST) Outbound DoorbellISH To HOST (ISH2HOST_DOORBELL_HOST) Outbound Inter Processor Message 1 From ISH To HOST (ISH2HOST_MSG1_HOST) Remap0 For HOST (REMAP0_HOST) Remap1 For HOST (REMAP1_HOST) Remap2 For HOST (REMAP2_HOST) Remap3 For HOST (REMAP3_HOST) D0i3 Control For HOST (IPC_d0i3C_HOST)
HOST Firmware Status (ISH_HOST_FWSTS_HOST)
HOST Communication (HOST_COMM_HOST)
Inbound DoorbellHOST To ISH (HOST2ISH_DOORBELL_HOST)
Outbound DoorbellISH To HOST (ISH2HOST_DOORBELL_HOST)
Outbound Inter Processor Message 1 From ISH To HOST (ISH2HOST_MSG1_HOST)
Remap0 For HOST (REMAP0_HOST)
Remap1 For HOST (REMAP1_HOST)
Remap2 For HOST (REMAP2_HOST)
Remap3 For HOST (REMAP3_HOST)
D0i3 Control For HOST (IPC_d0i3C_HOST)
Integrated Sensor Hub (ISH) PCI Configuration
Integrated Sensor Hub (ISH) PCI Configuration Device Id And Vendor Id Register (DEVVENDID) Status And Command (STATUSCOMMAND) Revision Id And Class Code (REVCLASSCODE) Cache Line Latency Header And Bist (CLLATHEADERBIST) Base Address Register (BAR) Base Address Register High (BAR_HIGH) Base Address Register1 (BAR1) Base Address Register1 High (BAR1_HIGH) Subsystem Vendor And Subsystem Id (SUBSYSTEMID) Expansion Rom Base Address (EXPANSION_ROM_BASEADDR) Capabilities Pointer (CAPABILITYPTR) Interrupt Register (INTERRUPTREG) Pcie Capabilities Register (PCIECAPREG) Power Management Capability Id (POWERCAPID) Power Management Control And Status Register (PMECTRLSTATUS) Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD) Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG) Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG) Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG) D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG) General Purpose Read Write Register1 (GEN_PCI_REGRW1) General Purpose Read Write Register2 (GEN_PCI_REGRW2) General Purpose Read Write Register3 (GEN_PCI_REGRW3) General Purpose Read Write Register4 (GEN_PCI_REGRW4) General Purpose Input Register (GEN_INPUT_REG) Msix Capability Register (MSIX_CAP_REG) Msix Table Pointer (MSIX_TABLE_PTR) Msix Pba Pointer (MSIX_PBA_PTR) Msi Capability Register (MSI_CAP_REG) Msi Message Low Address (MSI_ADDR_LOW) Msi Message High Address (MSI_ADDR_HIGH) Msi Message Data (MSI_MSG_DATA) Msi Mask Register (MSI_MASK) Msi Pending Register (MSI_PENDING) Ltr Capability Header Register (LTR_CAP_HEAD) Ltr Max Snoop Non Snoop Latency Register (MAX_LATENCY_REGISTER)
Device Id And Vendor Id Register (DEVVENDID)
Status And Command (STATUSCOMMAND)
Revision Id And Class Code (REVCLASSCODE)
Cache Line Latency Header And Bist (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Subsystem Vendor And Subsystem Id (SUBSYSTEMID)
Expansion Rom Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Pcie Capabilities Register (PCIECAPREG)
Power Management Capability Id (POWERCAPID)
Power Management Control And Status Register (PMECTRLSTATUS)
Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD)
Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG)
Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG)
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write Register1 (GEN_PCI_REGRW1)
General Purpose Read Write Register2 (GEN_PCI_REGRW2)
General Purpose Read Write Register3 (GEN_PCI_REGRW3)
General Purpose Read Write Register4 (GEN_PCI_REGRW4)
General Purpose Input Register (GEN_INPUT_REG)
Msix Capability Register (MSIX_CAP_REG)
Msix Table Pointer (MSIX_TABLE_PTR)
Msix Pba Pointer (MSIX_PBA_PTR)
Msi Capability Register (MSI_CAP_REG)
Msi Message Low Address (MSI_ADDR_LOW)
Msi Message High Address (MSI_ADDR_HIGH)
Msi Message Data (MSI_MSG_DATA)
Msi Mask Register (MSI_MASK)
Msi Pending Register (MSI_PENDING)
Ltr Capability Header Register (LTR_CAP_HEAD)
Ltr Max Snoop Non Snoop Latency Register (MAX_LATENCY_REGISTER)
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) MMIO DEVIDLE Control (HECI1_DEVIDLEC) Host Enhanced Extend Register Status (HECI1_ENH_HERS) Host Enhanced Extend Register DW1 (HECI1_ENH_HER1) Host Enhanced Extend Register DW2 (HECI1_ENH_HER2) Host Enhanced Extend Register DW3 (HECI1_ENH_HER3) Host Enhanced Extend Register DW4 (HECI1_ENH_HER4) Host Enhanced Extend Register DW5 (HECI1_ENH_HER5) Host Enhanced Extend Register DW6 (HECI1_ENH_HER6) Host Enhanced Extend Register DW7 (HECI1_ENH_HER7) Host Enhanced Extend Register DW8 (HECI1_ENH_HER8) Host Enhanced Extend Register DW9 (HECI1_ENH_HER9) Host Enhanced Extend Register DW10 (HECI1_ENH_HER10) Host Enhanced Extend Register DW11 (HECI1_ENH_HER11) Host Enhanced Extend Register DW12 (HECI1_ENH_HER12)
DEVIDLE Control (HECI1_DEVIDLEC)
Host Enhanced Extend Register Status (HECI1_ENH_HERS)
Host Enhanced Extend Register DW1 (HECI1_ENH_HER1)
Host Enhanced Extend Register DW2 (HECI1_ENH_HER2)
Host Enhanced Extend Register DW3 (HECI1_ENH_HER3)
Host Enhanced Extend Register DW4 (HECI1_ENH_HER4)
Host Enhanced Extend Register DW5 (HECI1_ENH_HER5)
Host Enhanced Extend Register DW6 (HECI1_ENH_HER6)
Host Enhanced Extend Register DW7 (HECI1_ENH_HER7)
Host Enhanced Extend Register DW8 (HECI1_ENH_HER8)
Host Enhanced Extend Register DW9 (HECI1_ENH_HER9)
Host Enhanced Extend Register DW10 (HECI1_ENH_HER10)
Host Enhanced Extend Register DW11 (HECI1_ENH_HER11)
Host Enhanced Extend Register DW12 (HECI1_ENH_HER12)
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel(R) Management Engine Interface (MEI) PCI Configuration HECI ID (HECI1_ID) HECI Command (HECI1_CMD) HECI Status (HECI1_STS) Revision ID And Class Code (HECI1_RID_CC) Cache Line Size (HECI1_CLS) Master Latency Timer (HECI1_MLT) Header Type (HECI1_HTYPE) Built In Self-Test (HECI1_BIST) HECI MMIO Base Address Low (HECI1_MMIO_MBAR_LO) HECI MMIO Base Address High (HECI1_MMIO_MBAR_HI) Sub System Identifiers (HECI1_SS) Capabilities Pointer (HECI1_CAP) Interrupt Information (HECI1_INTR) Minimum Grant (HECI1_MGNT) Maximum Latency (HECI1_MLAT) Host Firmware Status (HECI1_HFS) Miscellaneous Shadow (HECI1_MISC_SHDW) General Status Shadow 1 (HECI1_GS_SHDW1) Host General Status (HECI1_H_GS1) PCI Power Management Capability ID (HECI1_PID) PCI Power Management Capabilities (HECI1_PC) PCI Power Management Control And Status (HECI1_PMCS) General Status Shadow 2 (HECI1_GS_SHDW2) General Status Shadow 3 (HECI1_GS_SHDW3) General Status Shadow 4 (HECI1_GS_SHDW4) General Status Shadow 5 (HECI1_GS_SHDW5) Host General Status 2 (HECI1_H_GS2) Host General Status 3 (HECI1_H_GS3) Message Signaled Interrupt Identifiers (HECI1_MID) Message Signaled Interrupt Message Control (HECI1_MC) Message Signaled Interrupt Message Address (HECI1_MA) Message Signaled Interrupt Upper Address (HECI1_MUA) Message Signaled Interrupt Message Data (HECI1_MD) HECI Interrupt Delivery Mode (HECI1_HIDM) Vendor Specific Capability Register (HECI1_VSCR) Vendor Specific Extended Capability Register (HECI1_VSEC) SW LTR Pointer Register (HECI1_SWLTRPTR) Device Idle Pointer Register (HECI1_DEVIDLEPTR) Device Idle Power On Latency (HECI1_DEVIDLEPOL) DevIdle Power Control Enabled Register (HECI1_PWRCTRLEN) Host Extend Register Status (HECI1_HERS) Host Extend Register DW1 (HECI1_HER1) Host Extend Register DW2 (HECI1_HER2) Host Extend Register DW3 (HECI1_HER3) Host Extend Register DW4 (HECI1_HER4) Host Extend Register DW5 (HECI1_HER5) Host Extend Register DW6 (HECI1_HER6) Host Extend Register DW7 (HECI1_HER7) Host Extend Register DW8 (HECI1_HER8)
HECI ID (HECI1_ID)
HECI Command (HECI1_CMD)
HECI Status (HECI1_STS)
Revision ID And Class Code (HECI1_RID_CC)
Cache Line Size (HECI1_CLS)
Master Latency Timer (HECI1_MLT)
Header Type (HECI1_HTYPE)
Built In Self-Test (HECI1_BIST)
HECI MMIO Base Address Low (HECI1_MMIO_MBAR_LO)
HECI MMIO Base Address High (HECI1_MMIO_MBAR_HI)
Sub System Identifiers (HECI1_SS)
Capabilities Pointer (HECI1_CAP)
Interrupt Information (HECI1_INTR)
Minimum Grant (HECI1_MGNT)
Maximum Latency (HECI1_MLAT)
Host Firmware Status (HECI1_HFS)
Miscellaneous Shadow (HECI1_MISC_SHDW)
General Status Shadow 1 (HECI1_GS_SHDW1)
Host General Status (HECI1_H_GS1)
PCI Power Management Capability ID (HECI1_PID)
PCI Power Management Capabilities (HECI1_PC)
PCI Power Management Control And Status (HECI1_PMCS)
General Status Shadow 2 (HECI1_GS_SHDW2)
General Status Shadow 3 (HECI1_GS_SHDW3)
General Status Shadow 4 (HECI1_GS_SHDW4)
General Status Shadow 5 (HECI1_GS_SHDW5)
Host General Status 2 (HECI1_H_GS2)
Host General Status 3 (HECI1_H_GS3)
Message Signaled Interrupt Identifiers (HECI1_MID)
Message Signaled Interrupt Message Control (HECI1_MC)
Message Signaled Interrupt Message Address (HECI1_MA)
Message Signaled Interrupt Upper Address (HECI1_MUA)
Message Signaled Interrupt Message Data (HECI1_MD)
HECI Interrupt Delivery Mode (HECI1_HIDM)
Vendor Specific Capability Register (HECI1_VSCR)
Vendor Specific Extended Capability Register (HECI1_VSEC)
SW LTR Pointer Register (HECI1_SWLTRPTR)
Device Idle Pointer Register (HECI1_DEVIDLEPTR)
Device Idle Power On Latency (HECI1_DEVIDLEPOL)
DevIdle Power Control Enabled Register (HECI1_PWRCTRLEN)
Host Extend Register Status (HECI1_HERS)
Host Extend Register DW1 (HECI1_HER1)
Host Extend Register DW2 (HECI1_HER2)
Host Extend Register DW3 (HECI1_HER3)
Host Extend Register DW4 (HECI1_HER4)
Host Extend Register DW5 (HECI1_HER5)
Host Extend Register DW6 (HECI1_HER6)
Host Extend Register DW7 (HECI1_HER7)
Host Extend Register DW8 (HECI1_HER8)
Intel® High Definition Audio MMIO
Intel® High Definition Audio MMIO Global Capabilities (GCAP) Minor Version (VMIN) Major Version (VMAJ) Output Payload Capability (OUTPAY) Input Payload Capability (INPAY) Global Control (GCTL) Wake Enable (WAKEEN) Wake Status (WAKESTS) Global Status (GSTS) Global Capabilities 2 (GCAP2) Linked List Capabilities Header (LLCH) Output Stream Payload Capability (OUTSTRMPAY) Input Stream Payload Capability (INSTRMPAY) Interrupt Control (INTCTL) Interrupt Status (INTSTS) Wall Clock Counter (WALCLK) Stream Synchronization (SSYNC) CORB Lower Base Address (CORBLBASE) CORB Upper Base Address (CORBUBASE) CORB Write Pointer (CORBWP) CORB Read Pointer (CORBRP) CORB Control (CORBCTL) CORB Status (CORBSTS) CORB Size (CORBSIZE) Immediate Command (IC) Immediate Response (IR) Immediate Command Status (ICS) DMA Position Lower Base Address (DPLBASE) DMA Position Upper Base Address (DPUBASE) Input Stream Descriptor x Control (ISD0CTL_B0) Input Stream Descriptor x Control (ISD0CTL_B2) Input Stream Descriptor x Status (ISD0STS) Input Stream Descriptor x Link Position in Buffer (ISD0LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD0CBL) Input Stream Descriptor x Last Valid Index (ISD0LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD0FIFOW) Input Stream Descriptor x FIFO Size (ISD0FIFOS) Input Stream Descriptor x Format (ISD0FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD0BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD0BDLPUBA) Input Stream Descriptor x Control (ISD1CTL_B0) Input Stream Descriptor x Control (ISD1CTL_B2) Input Stream Descriptor x Status (ISD1STS) Input Stream Descriptor x Link Position in Buffer (ISD1LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD1CBL) Input Stream Descriptor x Last Valid Index (ISD1LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD1FIFOW) Input Stream Descriptor x FIFO Size (ISD1FIFOS) Input Stream Descriptor x Format (ISD1FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD1BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD1BDLPUBA) Input Stream Descriptor x Control (ISD2CTL_B0) Input Stream Descriptor x Control (ISD2CTL_B2) Input Stream Descriptor x Status (ISD2STS) Input Stream Descriptor x Link Position in Buffer (ISD2LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD2CBL) Input Stream Descriptor x Last Valid Index (ISD2LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD2FIFOW) Input Stream Descriptor x FIFO Size (ISD2FIFOS) Input Stream Descriptor x Format (ISD2FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD2BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD2BDLPUBA) Input Stream Descriptor x Control (ISD3CTL_B0) Input Stream Descriptor x Control (ISD3CTL_B2) Input Stream Descriptor x Status (ISD3STS) Input Stream Descriptor x Link Position in Buffer (ISD3LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD3CBL) Input Stream Descriptor x Last Valid Index (ISD3LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD3FIFOW) Input Stream Descriptor x FIFO Size (ISD3FIFOS) Input Stream Descriptor x Format (ISD3FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD3BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD3BDLPUBA) Input Stream Descriptor x Control (ISD4CTL_B0) Input Stream Descriptor x Control (ISD4CTL_B2) Input Stream Descriptor x Status (ISD4STS) Input Stream Descriptor x Link Position in Buffer (ISD4LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD4CBL) Input Stream Descriptor x Last Valid Index (ISD4LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD4FIFOW) Input Stream Descriptor x FIFO Size (ISD4FIFOS) Input Stream Descriptor x Format (ISD4FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD4BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD4BDLPUBA) Input Stream Descriptor x Control (ISD5CTL_B0) Input Stream Descriptor x Control (ISD5CTL_B2) Input Stream Descriptor x Status (ISD5STS) Input Stream Descriptor x Cyclic Buffer Length (ISD5CBL) Input Stream Descriptor x Last Valid Index (ISD5LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD5FIFOW) Input Stream Descriptor x FIFO Size (ISD5FIFOS) Input Stream Descriptor x Format (ISD5FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD5BDLPUBA) Input Stream Descriptor x Control (ISD6CTL_B0) Input Stream Descriptor x Control (ISD6CTL_B2) Input Stream Descriptor x Status (ISD6STS) Input Stream Descriptor x Link Position in Buffer (ISD6LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD6CBL) Input Stream Descriptor x Last Valid Index (ISD6LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD6FIFOW) Input Stream Descriptor x FIFO Size (ISD6FIFOS) Input Stream Descriptor x Format (ISD6FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD6BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD6BDLPUBA) Input Stream Descriptor x Control (ISD7CTL_B0) Input Stream Descriptor x Control (ISD7CTL_B2) Input Stream Descriptor x Status (ISD7STS) Input Stream Descriptor x Link Position in Buffer (ISD7LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD7CBL) Input Stream Descriptor x Last Valid Index (ISD7LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD7FIFOW) Input Stream Descriptor x FIFO Size (ISD7FIFOS) Input Stream Descriptor x Format (ISD7FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD7BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD7BDLPUBA) Input Stream Descriptor x Control (ISD8CTL_B0) Input Stream Descriptor x Control (ISD8CTL_B2) Input Stream Descriptor x Status (ISD8STS) Input Stream Descriptor x Link Position in Buffer (ISD8LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD8CBL) Input Stream Descriptor x Last Valid Index (ISD8LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD8FIFOW) Input Stream Descriptor x FIFO Size (ISD8FIFOS) Input Stream Descriptor x Format (ISD8FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD8BDLPUBA) Input Stream Descriptor x Control (ISD9CTL_B0) Input Stream Descriptor x Control (ISD9CTL_B2) Input Stream Descriptor x Status (ISD9STS) Input Stream Descriptor x Cyclic Buffer Length (ISD9CBL) Input Stream Descriptor x Last Valid Index (ISD9LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD9FIFOW) Input Stream Descriptor x FIFO Size (ISD9FIFOS) Input Stream Descriptor x Format (ISD9FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD9BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD9BDLPUBA) Output Stream Descriptor x Control (OSD0CTL_B0) Output Stream Descriptor x Control (OSD0CTL_B2) Output Stream Descriptor x Status (OSD0STS) Output Stream Descriptor x Link Position in Buffer (OSD0LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD0CBL) Output Stream Descriptor x Last Valid Index (OSD0LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD0FIFOW) Output Stream Descriptor x FIFO Size (OSD0FIFOS) Output Stream Descriptor x Format (OSD0FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD0BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD0BDLPUBA) Output Stream Descriptor x Control (OSD1CTL_B0) Output Stream Descriptor x Control (OSD1CTL_B2) Output Stream Descriptor x Status (OSD1STS) Output Stream Descriptor x Link Position in Buffer (OSD1LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD1CBL) Output Stream Descriptor x Last Valid Index (OSD1LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD1FIFOW) Output Stream Descriptor x FIFO Size (OSD1FIFOS) Output Stream Descriptor x Format (OSD1FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD1BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD1BDLPUBA) Output Stream Descriptor x Control (OSD2CTL_B0) Output Stream Descriptor x Control (OSD2CTL_B2) Output Stream Descriptor x Status (OSD2STS) Output Stream Descriptor x Link Position in Buffer (OSD2LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD2CBL) Output Stream Descriptor x Last Valid Index (OSD2LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD2FIFOW) Output Stream Descriptor x FIFO Size (OSD2FIFOS) Output Stream Descriptor x Format (OSD2FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD2BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD2BDLPUBA) Output Stream Descriptor x Control (OSD3CTL_B0) Output Stream Descriptor x Control (OSD3CTL_B2) Output Stream Descriptor x Status (OSD3STS) Output Stream Descriptor x Link Position in Buffer (OSD3LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD3CBL) Output Stream Descriptor x Last Valid Index (OSD3LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD3FIFOW) Output Stream Descriptor x FIFO Size (OSD3FIFOS) Output Stream Descriptor x Format (OSD3FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD3BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD3BDLPUBA) Output Stream Descriptor x Control (OSD4CTL_B0) Output Stream Descriptor x Control (OSD4CTL_B2) Output Stream Descriptor x Status (OSD4STS) Output Stream Descriptor x Link Position in Buffer (OSD4LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD4CBL) Output Stream Descriptor x Last Valid Index (OSD4LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD4FIFOW) Output Stream Descriptor x FIFO Size (OSD4FIFOS) Output Stream Descriptor x Format (OSD4FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD4BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD4BDLPUBA) Output Stream Descriptor x Control (OSD5CTL_B0) Output Stream Descriptor x Control (OSD5CTL_B2) Output Stream Descriptor x Status (OSD5STS) Output Stream Descriptor x Link Position in Buffer (OSD5LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD5CBL) Output Stream Descriptor x Last Valid Index (OSD5LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD5FIFOW) Output Stream Descriptor x FIFO Size (OSD5FIFOS) Output Stream Descriptor x Format (OSD5FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD5BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD5BDLPUBA) Output Stream Descriptor x Control (OSD6CTL_B0) Output Stream Descriptor x Control (OSD6CTL_B2) Output Stream Descriptor x Status (OSD6STS) Output Stream Descriptor x Link Position in Buffer (OSD6LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD6CBL) Output Stream Descriptor x Last Valid Index (OSD6LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD6FIFOW) Output Stream Descriptor x FIFO Size (OSD6FIFOS) Output Stream Descriptor x Format (OSD6FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD6BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD6BDLPUBA) Output Stream Descriptor x Control (OSD7CTL_B0) Output Stream Descriptor x Control (OSD7CTL_B2) Output Stream Descriptor x Status (OSD7STS) Output Stream Descriptor x Link Position in Buffer (OSD7LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD7CBL) Output Stream Descriptor x Last Valid Index (OSD7LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD7FIFOW) Output Stream Descriptor x FIFO Size (OSD7FIFOS) Output Stream Descriptor x Format (OSD7FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD7BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD7BDLPUBA) Output Stream Descriptor x Control (OSD8CTL_B0) Output Stream Descriptor x Control (OSD8CTL_B2) Output Stream Descriptor x Status (OSD8STS) Output Stream Descriptor x Link Position in Buffer (OSD8LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD8CBL) Output Stream Descriptor x Last Valid Index (OSD8LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD8FIFOW) Output Stream Descriptor x FIFO Size (OSD8FIFOS) Output Stream Descriptor x Format (OSD8FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD8BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD8BDLPUBA) DMA Resume Capability Header (DRSMCH) DMA Resume Control (DRSMCTL) Input Stream Descriptor x DMA Position in Buffer Resume (ISD0DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD1DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD2DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD3DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD4DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD5DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD6DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD7DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD8DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD9DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (OSD0DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (OSD1DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (OSD2DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (OSD3DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (OSD4DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (OSD5DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (OSD6DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (OSD7DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (OSD8DPIBR) Software Position Based FIFO Capability Header (SPBFCH) Software Position Based FIFO Control (SPBFCTL) Input / Output Stream Descriptor x Software Position in Buffer (ISD0SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD0MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (ISD1SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD1MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (ISD2SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD2MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (ISD3SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD3MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (ISD4SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD4MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (ISD5SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD5MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (ISD6SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD6MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (ISD7SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD7MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (ISD8SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD8MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (ISD9SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD9MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (OSD0SPIB) Input / Output Stream Descriptor x Max FIFO Size (OSD0MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (OSD1SPIB) Input / Output Stream Descriptor x Max FIFO Size (OSD1MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (OSD2SPIB) Input / Output Stream Descriptor x Max FIFO Size (OSD2MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (OSD3SPIB) Input / Output Stream Descriptor x Max FIFO Size (OSD3MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (OSD4SPIB) Input / Output Stream Descriptor x Max FIFO Size (OSD4MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (OSD5SPIB) Input / Output Stream Descriptor x Max FIFO Size (OSD5MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (OSD6SPIB) Input / Output Stream Descriptor x Max FIFO Size (OSD6MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (OSD7SPIB) Input / Output Stream Descriptor x Max FIFO Size (OSD7MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (OSD8SPIB) Input / Output Stream Descriptor x Max FIFO Size (OSD8MAXFIFOS) Processing Pipe Capability Header (PPCH) Processing Pipe Control (PPCTL) Processing Pipe Status (PPSTS) Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC0LLPL) Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC0LLPU) Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC0LDPL) Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC0LDPU) Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC1LLPL) Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC1LLPU) Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC1LDPL) Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC1LDPU) Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC2LLPL) Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC2LLPU) Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC2LDPL) Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC2LDPU) Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC3LLPL) Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC3LLPU) Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC3LDPL) Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC3LDPU) Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC4LLPL) Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC4LLPU) Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC4LDPL) Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC4LDPU) Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC5LLPL) Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC5LLPU) Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC5LDPL) Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC5LDPU) Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC6LLPL) Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC6LLPU) Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC6LDPL) Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC6LDPU) Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC7LLPL) Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC7LLPU) Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC7LDPL) Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC7LDPU) Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC8LLPL) Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC8LLPU) Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC8LDPL) Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC8LDPU) Input / Output Processing Pipes Link Connection on Control (OPPLC0CTL) Input / Output Processing Pipes Link Connection on Format (OPPLC0FMT) Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC0LLPL) Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC0LLPU) Input / Output Processing Pipes Link Connection on Control (OPPLC1CTL) Input / Output Processing Pipes Link Connection on Format (OPPLC1FMT) Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC1LLPL) Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC1LLPU) Input / Output Processing Pipes Link Connection on Control (OPPLC2CTL) Input / Output Processing Pipes Link Connection on Format (OPPLC2FMT) Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC2LLPL) Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC2LLPU) Input / Output Processing Pipes Link Connection on Control (OPPLC3CTL) Input / Output Processing Pipes Link Connection on Format (OPPLC3FMT) Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC3LLPL) Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC3LLPU) Input / Output Processing Pipes Link Connection on Control (OPPLC4CTL) Input / Output Processing Pipes Link Connection on Format (OPPLC4FMT) Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC4LLPL) Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC4LLPU) Input / Output Processing Pipes Link Connection on Control (OPPLC5CTL) Input / Output Processing Pipes Link Connection on Format (OPPLC5FMT) Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC5LLPL) Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC5LLPU) Input / Output Processing Pipes Link Connection on Control (OPPLC6CTL) Input / Output Processing Pipes Link Connection on Format (OPPLC6FMT) Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC6LLPL) Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC6LLPU) Input / Output Processing Pipes Link Connection on Control (OPPLC7CTL) Input / Output Processing Pipes Link Connection on Format (OPPLC7FMT) Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC7LLPL) Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC7LLPU) Input / Output Processing Pipes Link Connection on Control (OPPLC8CTL) Input / Output Processing Pipes Link Connection on Format (OPPLC8FMT) Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC8LLPL) Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC8LLPU) Multiple Links Capability Header (MLCH) Multiple Links Capability Declaration (MLCD) Link x Capabilities (LCAP0) Link x Control (LCTL0) Link x SDI IDentifiers (LSDIID0) Link x Per Stream Output Overhead (LPSOO0) Link x Per Stream Input Overhead (LPSIO0) Link x Wall Frame Counter (LWALFC0) Link x 6 MHz Output Payload Capability (LOUTPAY60) Link x 12 MHz Output Payload Capability (LOUTPAY120) Link x 24 MHz Output Payload Capability (LOUTPAY240) Link x 48 MHz Output Payload Capability (LOUTPAY480) Link x 96 MHz Output Payload Capability (LOUTPAY960) Link x 192 MHz Output Payload Capability (LOUTPAY1920) Link x 6 MHz Input Payload Capability (LINPAY60) Link x 12 MHz Input Payload Capability (LINPAY120) Link x 24 MHz Input Payload Capability (LINPAY240) Link x 48 MHz Input Payload Capability (LINPAY480) Link x 96 MHz Input Payload Capability (LINPAY960) Link x 192 MHz Input Payload Capability (LINPAY1920) Link x Capabilities (LCAP1) Link x Control (LCTL1) Link x SDI IDentifiers (LSDIID1) Link x Per Stream Output Overhead (LPSOO1) Link x Per Stream Input Overhead (LPSIO1) Link x Wall Frame Counter (LWALFC1) Link x 6 MHz Output Payload Capability (LOUTPAY61) Link x 12 MHz Output Payload Capability (LOUTPAY121) Link x 24 MHz Output Payload Capability (LOUTPAY241) Link x 48 MHz Output Payload Capability (LOUTPAY481) Link x 96 MHz Output Payload Capability (LOUTPAY961) Link x 192 MHz Output Payload Capability (LOUTPAY1921) Link x 6 MHz Input Payload Capability (LINPAY61) Link x 12 MHz Input Payload Capability (LINPAY121) Link x 24 MHz Input Payload Capability (LINPAY241) Link x 48 MHz Input Payload Capability (LINPAY481) Link x 96 MHz Input Payload Capability (LINPAY961) Link x 192 MHz Input Payload Capability (LINPAY1921) Input / Output Stream Descriptor x DMA Position in Buffer (ISD0DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (ISD1DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (ISD2DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (ISD3DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (ISD4DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (ISD5DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (ISD6DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (ISD7DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (ISD8DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (ISD9DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (OSD0DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (OSD1DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (OSD3DPIB) Latency Tolerance Reporting Policy (LTRP) Input Stream Repeat Count (INRC) D0i3 Control (D0I3C) Power Transition Delay Control (PTDC) Function Configuration (FNCFG) Wall Clock Counter Alias (WALCLKA) Input/Output Stream Descriptor x Link Position in Buffer (ISD0LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (ISD1LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (ISD2LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (ISD3LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (ISD4LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (ISD5LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (ISD6LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (ISD7LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (ISD8LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (ISD9LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (OSD0LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (OSD1LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (OSD2LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (OSD3LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (OSD4LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (OSD5LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (OSD6LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (OSD7LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (OSD8LPIBA)
Global Capabilities (GCAP)
Minor Version (VMIN)
Major Version (VMAJ)
Output Payload Capability (OUTPAY)
Input Payload Capability (INPAY)
Global Control (GCTL)
Wake Enable (WAKEEN)
Wake Status (WAKESTS)
Global Status (GSTS)
Global Capabilities 2 (GCAP2)
Linked List Capabilities Header (LLCH)
Output Stream Payload Capability (OUTSTRMPAY)
Input Stream Payload Capability (INSTRMPAY)
Interrupt Control (INTCTL)
Interrupt Status (INTSTS)
Wall Clock Counter (WALCLK)
Stream Synchronization (SSYNC)
CORB Lower Base Address (CORBLBASE)
CORB Upper Base Address (CORBUBASE)
CORB Write Pointer (CORBWP)
CORB Read Pointer (CORBRP)
CORB Control (CORBCTL)
CORB Status (CORBSTS)
CORB Size (CORBSIZE)
Immediate Command (IC)
Immediate Response (IR)
Immediate Command Status (ICS)
DMA Position Lower Base Address (DPLBASE)
DMA Position Upper Base Address (DPUBASE)
Input Stream Descriptor x Control (ISD0CTL_B0)
Input Stream Descriptor x Control (ISD0CTL_B2)
Input Stream Descriptor x Status (ISD0STS)
Input Stream Descriptor x Link Position in Buffer (ISD0LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD0CBL)
Input Stream Descriptor x Last Valid Index (ISD0LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD0FIFOW)
Input Stream Descriptor x FIFO Size (ISD0FIFOS)
Input Stream Descriptor x Format (ISD0FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD0BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD0BDLPUBA)
Input Stream Descriptor x Control (ISD1CTL_B0)
Input Stream Descriptor x Control (ISD1CTL_B2)
Input Stream Descriptor x Status (ISD1STS)
Input Stream Descriptor x Link Position in Buffer (ISD1LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD1CBL)
Input Stream Descriptor x Last Valid Index (ISD1LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD1FIFOW)
Input Stream Descriptor x FIFO Size (ISD1FIFOS)
Input Stream Descriptor x Format (ISD1FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD1BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD1BDLPUBA)
Input Stream Descriptor x Control (ISD2CTL_B0)
Input Stream Descriptor x Control (ISD2CTL_B2)
Input Stream Descriptor x Status (ISD2STS)
Input Stream Descriptor x Link Position in Buffer (ISD2LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD2CBL)
Input Stream Descriptor x Last Valid Index (ISD2LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD2FIFOW)
Input Stream Descriptor x FIFO Size (ISD2FIFOS)
Input Stream Descriptor x Format (ISD2FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD2BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD2BDLPUBA)
Input Stream Descriptor x Control (ISD3CTL_B0)
Input Stream Descriptor x Control (ISD3CTL_B2)
Input Stream Descriptor x Status (ISD3STS)
Input Stream Descriptor x Link Position in Buffer (ISD3LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD3CBL)
Input Stream Descriptor x Last Valid Index (ISD3LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD3FIFOW)
Input Stream Descriptor x FIFO Size (ISD3FIFOS)
Input Stream Descriptor x Format (ISD3FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD3BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD3BDLPUBA)
Input Stream Descriptor x Control (ISD4CTL_B0)
Input Stream Descriptor x Control (ISD4CTL_B2)
Input Stream Descriptor x Status (ISD4STS)
Input Stream Descriptor x Link Position in Buffer (ISD4LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD4CBL)
Input Stream Descriptor x Last Valid Index (ISD4LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD4FIFOW)
Input Stream Descriptor x FIFO Size (ISD4FIFOS)
Input Stream Descriptor x Format (ISD4FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD4BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD4BDLPUBA)
Input Stream Descriptor x Control (ISD5CTL_B0)
Input Stream Descriptor x Control (ISD5CTL_B2)
Input Stream Descriptor x Status (ISD5STS)
Input Stream Descriptor x Cyclic Buffer Length (ISD5CBL)
Input Stream Descriptor x Last Valid Index (ISD5LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD5FIFOW)
Input Stream Descriptor x FIFO Size (ISD5FIFOS)
Input Stream Descriptor x Format (ISD5FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD5BDLPUBA)
Input Stream Descriptor x Control (ISD6CTL_B0)
Input Stream Descriptor x Control (ISD6CTL_B2)
Input Stream Descriptor x Status (ISD6STS)
Input Stream Descriptor x Link Position in Buffer (ISD6LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD6CBL)
Input Stream Descriptor x Last Valid Index (ISD6LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD6FIFOW)
Input Stream Descriptor x FIFO Size (ISD6FIFOS)
Input Stream Descriptor x Format (ISD6FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD6BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD6BDLPUBA)
Input Stream Descriptor x Control (ISD7CTL_B0)
Input Stream Descriptor x Control (ISD7CTL_B2)
Input Stream Descriptor x Status (ISD7STS)
Input Stream Descriptor x Link Position in Buffer (ISD7LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD7CBL)
Input Stream Descriptor x Last Valid Index (ISD7LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD7FIFOW)
Input Stream Descriptor x FIFO Size (ISD7FIFOS)
Input Stream Descriptor x Format (ISD7FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD7BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD7BDLPUBA)
Input Stream Descriptor x Control (ISD8CTL_B0)
Input Stream Descriptor x Control (ISD8CTL_B2)
Input Stream Descriptor x Status (ISD8STS)
Input Stream Descriptor x Link Position in Buffer (ISD8LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD8CBL)
Input Stream Descriptor x Last Valid Index (ISD8LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD8FIFOW)
Input Stream Descriptor x FIFO Size (ISD8FIFOS)
Input Stream Descriptor x Format (ISD8FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD8BDLPUBA)
Input Stream Descriptor x Control (ISD9CTL_B0)
Input Stream Descriptor x Control (ISD9CTL_B2)
Input Stream Descriptor x Status (ISD9STS)
Input Stream Descriptor x Cyclic Buffer Length (ISD9CBL)
Input Stream Descriptor x Last Valid Index (ISD9LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD9FIFOW)
Input Stream Descriptor x FIFO Size (ISD9FIFOS)
Input Stream Descriptor x Format (ISD9FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD9BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD9BDLPUBA)
Output Stream Descriptor x Control (OSD0CTL_B0)
Output Stream Descriptor x Control (OSD0CTL_B2)
Output Stream Descriptor x Status (OSD0STS)
Output Stream Descriptor x Link Position in Buffer (OSD0LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD0CBL)
Output Stream Descriptor x Last Valid Index (OSD0LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD0FIFOW)
Output Stream Descriptor x FIFO Size (OSD0FIFOS)
Output Stream Descriptor x Format (OSD0FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD0BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD0BDLPUBA)
Output Stream Descriptor x Control (OSD1CTL_B0)
Output Stream Descriptor x Control (OSD1CTL_B2)
Output Stream Descriptor x Status (OSD1STS)
Output Stream Descriptor x Link Position in Buffer (OSD1LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD1CBL)
Output Stream Descriptor x Last Valid Index (OSD1LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD1FIFOW)
Output Stream Descriptor x FIFO Size (OSD1FIFOS)
Output Stream Descriptor x Format (OSD1FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD1BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD1BDLPUBA)
Output Stream Descriptor x Control (OSD2CTL_B0)
Output Stream Descriptor x Control (OSD2CTL_B2)
Output Stream Descriptor x Status (OSD2STS)
Output Stream Descriptor x Link Position in Buffer (OSD2LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD2CBL)
Output Stream Descriptor x Last Valid Index (OSD2LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD2FIFOW)
Output Stream Descriptor x FIFO Size (OSD2FIFOS)
Output Stream Descriptor x Format (OSD2FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD2BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD2BDLPUBA)
Output Stream Descriptor x Control (OSD3CTL_B0)
Output Stream Descriptor x Control (OSD3CTL_B2)
Output Stream Descriptor x Status (OSD3STS)
Output Stream Descriptor x Link Position in Buffer (OSD3LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD3CBL)
Output Stream Descriptor x Last Valid Index (OSD3LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD3FIFOW)
Output Stream Descriptor x FIFO Size (OSD3FIFOS)
Output Stream Descriptor x Format (OSD3FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD3BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD3BDLPUBA)
Output Stream Descriptor x Control (OSD4CTL_B0)
Output Stream Descriptor x Control (OSD4CTL_B2)
Output Stream Descriptor x Status (OSD4STS)
Output Stream Descriptor x Link Position in Buffer (OSD4LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD4CBL)
Output Stream Descriptor x Last Valid Index (OSD4LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD4FIFOW)
Output Stream Descriptor x FIFO Size (OSD4FIFOS)
Output Stream Descriptor x Format (OSD4FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD4BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD4BDLPUBA)
Output Stream Descriptor x Control (OSD5CTL_B0)
Output Stream Descriptor x Control (OSD5CTL_B2)
Output Stream Descriptor x Status (OSD5STS)
Output Stream Descriptor x Link Position in Buffer (OSD5LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD5CBL)
Output Stream Descriptor x Last Valid Index (OSD5LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD5FIFOW)
Output Stream Descriptor x FIFO Size (OSD5FIFOS)
Output Stream Descriptor x Format (OSD5FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD5BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD5BDLPUBA)
Output Stream Descriptor x Control (OSD6CTL_B0)
Output Stream Descriptor x Control (OSD6CTL_B2)
Output Stream Descriptor x Status (OSD6STS)
Output Stream Descriptor x Link Position in Buffer (OSD6LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD6CBL)
Output Stream Descriptor x Last Valid Index (OSD6LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD6FIFOW)
Output Stream Descriptor x FIFO Size (OSD6FIFOS)
Output Stream Descriptor x Format (OSD6FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD6BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD6BDLPUBA)
Output Stream Descriptor x Control (OSD7CTL_B0)
Output Stream Descriptor x Control (OSD7CTL_B2)
Output Stream Descriptor x Status (OSD7STS)
Output Stream Descriptor x Link Position in Buffer (OSD7LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD7CBL)
Output Stream Descriptor x Last Valid Index (OSD7LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD7FIFOW)
Output Stream Descriptor x FIFO Size (OSD7FIFOS)
Output Stream Descriptor x Format (OSD7FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD7BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD7BDLPUBA)
Output Stream Descriptor x Control (OSD8CTL_B0)
Output Stream Descriptor x Control (OSD8CTL_B2)
Output Stream Descriptor x Status (OSD8STS)
Output Stream Descriptor x Link Position in Buffer (OSD8LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD8CBL)
Output Stream Descriptor x Last Valid Index (OSD8LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD8FIFOW)
Output Stream Descriptor x FIFO Size (OSD8FIFOS)
Output Stream Descriptor x Format (OSD8FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD8BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD8BDLPUBA)
DMA Resume Capability Header (DRSMCH)
DMA Resume Control (DRSMCTL)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD0DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD1DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD2DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD3DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD4DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD5DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD6DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD7DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD8DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD9DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (OSD0DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (OSD1DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (OSD2DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (OSD3DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (OSD4DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (OSD5DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (OSD6DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (OSD7DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (OSD8DPIBR)
Software Position Based FIFO Capability Header (SPBFCH)
Software Position Based FIFO Control (SPBFCTL)
Input / Output Stream Descriptor x Software Position in Buffer (ISD0SPIB)
Input / Output Stream Descriptor x Max FIFO Size (ISD0MAXFIFOS)
Input / Output Stream Descriptor x Software Position in Buffer (ISD1SPIB)
Input / Output Stream Descriptor x Max FIFO Size (ISD1MAXFIFOS)
Input / Output Stream Descriptor x Software Position in Buffer (ISD2SPIB)
Input / Output Stream Descriptor x Max FIFO Size (ISD2MAXFIFOS)
Input / Output Stream Descriptor x Software Position in Buffer (ISD3SPIB)
Input / Output Stream Descriptor x Max FIFO Size (ISD3MAXFIFOS)
Input / Output Stream Descriptor x Software Position in Buffer (ISD4SPIB)
Input / Output Stream Descriptor x Max FIFO Size (ISD4MAXFIFOS)
Input / Output Stream Descriptor x Software Position in Buffer (ISD5SPIB)
Input / Output Stream Descriptor x Max FIFO Size (ISD5MAXFIFOS)
Input / Output Stream Descriptor x Software Position in Buffer (ISD6SPIB)
Input / Output Stream Descriptor x Max FIFO Size (ISD6MAXFIFOS)
Input / Output Stream Descriptor x Software Position in Buffer (ISD7SPIB)
Input / Output Stream Descriptor x Max FIFO Size (ISD7MAXFIFOS)
Input / Output Stream Descriptor x Software Position in Buffer (ISD8SPIB)
Input / Output Stream Descriptor x Max FIFO Size (ISD8MAXFIFOS)
Input / Output Stream Descriptor x Software Position in Buffer (ISD9SPIB)
Input / Output Stream Descriptor x Max FIFO Size (ISD9MAXFIFOS)
Input / Output Stream Descriptor x Software Position in Buffer (OSD0SPIB)
Input / Output Stream Descriptor x Max FIFO Size (OSD0MAXFIFOS)
Input / Output Stream Descriptor x Software Position in Buffer (OSD1SPIB)
Input / Output Stream Descriptor x Max FIFO Size (OSD1MAXFIFOS)
Input / Output Stream Descriptor x Software Position in Buffer (OSD2SPIB)
Input / Output Stream Descriptor x Max FIFO Size (OSD2MAXFIFOS)
Input / Output Stream Descriptor x Software Position in Buffer (OSD3SPIB)
Input / Output Stream Descriptor x Max FIFO Size (OSD3MAXFIFOS)
Input / Output Stream Descriptor x Software Position in Buffer (OSD4SPIB)
Input / Output Stream Descriptor x Max FIFO Size (OSD4MAXFIFOS)
Input / Output Stream Descriptor x Software Position in Buffer (OSD5SPIB)
Input / Output Stream Descriptor x Max FIFO Size (OSD5MAXFIFOS)
Input / Output Stream Descriptor x Software Position in Buffer (OSD6SPIB)
Input / Output Stream Descriptor x Max FIFO Size (OSD6MAXFIFOS)
Input / Output Stream Descriptor x Software Position in Buffer (OSD7SPIB)
Input / Output Stream Descriptor x Max FIFO Size (OSD7MAXFIFOS)
Input / Output Stream Descriptor x Software Position in Buffer (OSD8SPIB)
Input / Output Stream Descriptor x Max FIFO Size (OSD8MAXFIFOS)
Processing Pipe Capability Header (PPCH)
Processing Pipe Control (PPCTL)
Processing Pipe Status (PPSTS)
Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC0LLPL)
Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC0LLPU)
Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC0LDPL)
Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC0LDPU)
Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC1LLPL)
Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC1LLPU)
Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC1LDPL)
Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC1LDPU)
Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC2LLPL)
Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC2LLPU)
Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC2LDPL)
Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC2LDPU)
Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC3LLPL)
Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC3LLPU)
Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC3LDPL)
Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC3LDPU)
Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC4LLPL)
Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC4LLPU)
Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC4LDPL)
Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC4LDPU)
Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC5LLPL)
Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC5LLPU)
Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC5LDPL)
Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC5LDPU)
Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC6LLPL)
Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC6LLPU)
Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC6LDPL)
Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC6LDPU)
Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC7LLPL)
Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC7LLPU)
Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC7LDPL)
Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC7LDPU)
Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC8LLPL)
Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC8LLPU)
Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC8LDPL)
Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC8LDPU)
Input / Output Processing Pipes Link Connection on Control (OPPLC0CTL)
Input / Output Processing Pipes Link Connection on Format (OPPLC0FMT)
Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC0LLPL)
Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC0LLPU)
Input / Output Processing Pipes Link Connection on Control (OPPLC1CTL)
Input / Output Processing Pipes Link Connection on Format (OPPLC1FMT)
Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC1LLPL)
Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC1LLPU)
Input / Output Processing Pipes Link Connection on Control (OPPLC2CTL)
Input / Output Processing Pipes Link Connection on Format (OPPLC2FMT)
Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC2LLPL)
Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC2LLPU)
Input / Output Processing Pipes Link Connection on Control (OPPLC3CTL)
Input / Output Processing Pipes Link Connection on Format (OPPLC3FMT)
Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC3LLPL)
Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC3LLPU)
Input / Output Processing Pipes Link Connection on Control (OPPLC4CTL)
Input / Output Processing Pipes Link Connection on Format (OPPLC4FMT)
Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC4LLPL)
Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC4LLPU)
Input / Output Processing Pipes Link Connection on Control (OPPLC5CTL)
Input / Output Processing Pipes Link Connection on Format (OPPLC5FMT)
Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC5LLPL)
Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC5LLPU)
Input / Output Processing Pipes Link Connection on Control (OPPLC6CTL)
Input / Output Processing Pipes Link Connection on Format (OPPLC6FMT)
Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC6LLPL)
Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC6LLPU)
Input / Output Processing Pipes Link Connection on Control (OPPLC7CTL)
Input / Output Processing Pipes Link Connection on Format (OPPLC7FMT)
Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC7LLPL)
Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC7LLPU)
Input / Output Processing Pipes Link Connection on Control (OPPLC8CTL)
Input / Output Processing Pipes Link Connection on Format (OPPLC8FMT)
Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC8LLPL)
Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC8LLPU)
Multiple Links Capability Header (MLCH)
Multiple Links Capability Declaration (MLCD)
Link x Capabilities (LCAP0)
Link x Control (LCTL0)
Link x SDI IDentifiers (LSDIID0)
Link x Per Stream Output Overhead (LPSOO0)
Link x Per Stream Input Overhead (LPSIO0)
Link x Wall Frame Counter (LWALFC0)
Link x 6 MHz Output Payload Capability (LOUTPAY60)
Link x 12 MHz Output Payload Capability (LOUTPAY120)
Link x 24 MHz Output Payload Capability (LOUTPAY240)
Link x 48 MHz Output Payload Capability (LOUTPAY480)
Link x 96 MHz Output Payload Capability (LOUTPAY960)
Link x 192 MHz Output Payload Capability (LOUTPAY1920)
Link x 6 MHz Input Payload Capability (LINPAY60)
Link x 12 MHz Input Payload Capability (LINPAY120)
Link x 24 MHz Input Payload Capability (LINPAY240)
Link x 48 MHz Input Payload Capability (LINPAY480)
Link x 96 MHz Input Payload Capability (LINPAY960)
Link x 192 MHz Input Payload Capability (LINPAY1920)
Link x Capabilities (LCAP1)
Link x Control (LCTL1)
Link x SDI IDentifiers (LSDIID1)
Link x Per Stream Output Overhead (LPSOO1)
Link x Per Stream Input Overhead (LPSIO1)
Link x Wall Frame Counter (LWALFC1)
Link x 6 MHz Output Payload Capability (LOUTPAY61)
Link x 12 MHz Output Payload Capability (LOUTPAY121)
Link x 24 MHz Output Payload Capability (LOUTPAY241)
Link x 48 MHz Output Payload Capability (LOUTPAY481)
Link x 96 MHz Output Payload Capability (LOUTPAY961)
Link x 192 MHz Output Payload Capability (LOUTPAY1921)
Link x 6 MHz Input Payload Capability (LINPAY61)
Link x 12 MHz Input Payload Capability (LINPAY121)
Link x 24 MHz Input Payload Capability (LINPAY241)
Link x 48 MHz Input Payload Capability (LINPAY481)
Link x 96 MHz Input Payload Capability (LINPAY961)
Link x 192 MHz Input Payload Capability (LINPAY1921)
Input / Output Stream Descriptor x DMA Position in Buffer (ISD0DPIB)
Input / Output Stream Descriptor x DMA Position in Buffer (ISD1DPIB)
Input / Output Stream Descriptor x DMA Position in Buffer (ISD2DPIB)
Input / Output Stream Descriptor x DMA Position in Buffer (ISD3DPIB)
Input / Output Stream Descriptor x DMA Position in Buffer (ISD4DPIB)
Input / Output Stream Descriptor x DMA Position in Buffer (ISD5DPIB)
Input / Output Stream Descriptor x DMA Position in Buffer (ISD6DPIB)
Input / Output Stream Descriptor x DMA Position in Buffer (ISD7DPIB)
Input / Output Stream Descriptor x DMA Position in Buffer (ISD8DPIB)
Input / Output Stream Descriptor x DMA Position in Buffer (ISD9DPIB)
Input / Output Stream Descriptor x DMA Position in Buffer (OSD0DPIB)
Input / Output Stream Descriptor x DMA Position in Buffer (OSD1DPIB)
Input / Output Stream Descriptor x DMA Position in Buffer (OSD3DPIB)
Latency Tolerance Reporting Policy (LTRP)
Input Stream Repeat Count (INRC)
D0i3 Control (D0I3C)
Power Transition Delay Control (PTDC)
Function Configuration (FNCFG)
Wall Clock Counter Alias (WALCLKA)
Input/Output Stream Descriptor x Link Position in Buffer (ISD0LPIBA)
Input/Output Stream Descriptor x Link Position in Buffer (ISD1LPIBA)
Input/Output Stream Descriptor x Link Position in Buffer (ISD2LPIBA)
Input/Output Stream Descriptor x Link Position in Buffer (ISD3LPIBA)
Input/Output Stream Descriptor x Link Position in Buffer (ISD4LPIBA)
Input/Output Stream Descriptor x Link Position in Buffer (ISD5LPIBA)
Input/Output Stream Descriptor x Link Position in Buffer (ISD6LPIBA)
Input/Output Stream Descriptor x Link Position in Buffer (ISD7LPIBA)
Input/Output Stream Descriptor x Link Position in Buffer (ISD8LPIBA)
Input/Output Stream Descriptor x Link Position in Buffer (ISD9LPIBA)
Input/Output Stream Descriptor x Link Position in Buffer (OSD0LPIBA)
Input/Output Stream Descriptor x Link Position in Buffer (OSD1LPIBA)
Input/Output Stream Descriptor x Link Position in Buffer (OSD2LPIBA)
Input/Output Stream Descriptor x Link Position in Buffer (OSD3LPIBA)
Input/Output Stream Descriptor x Link Position in Buffer (OSD4LPIBA)
Input/Output Stream Descriptor x Link Position in Buffer (OSD5LPIBA)
Input/Output Stream Descriptor x Link Position in Buffer (OSD6LPIBA)
Input/Output Stream Descriptor x Link Position in Buffer (OSD7LPIBA)
Input/Output Stream Descriptor x Link Position in Buffer (OSD8LPIBA)
Intel® High Definition Audio PCI Configuration
Intel® High Definition Audio PCI Configuration Vendor Identification (VID) Device Identification (DID) Command Register (CMD) Status Register (STS) Revision Identification (RID) Programming Interface (PI) Sub Class Code (SCC) Base Class Code (BCC) Cache Line Size (CLS) Latency Timer (LT) Header Type (HTYPE) Built-in Self Test (BIST) Intel HD Audio Lower Base Address (HDALBA) Intel HD Audio Upper Base Address (HDAUBA) Shadowed PCI Configuration Lower Base Address (SPCLBA) Shadowed PCI Configuration Upper Base Address (SPCUBA) DSP Subsystem Lower Base Address (DSPLBA) DSP Subsystem Upper Base Address (DSPUBA) Subsystem Vendor Identifier (SVID) Subsystem Identifier (SID) Capabilities Pointer (CAPPTR) Interrupt Line (INTLN) Interrupt Pin (INTPN) Power Management Identifiers (PID) Power Management Capabilities (PC) Power Management Control & Status (PCS) MSI Identifiers (MID) MSI Message Control (MMC) MSI Message Lower Address (MMLA) MSI Message Upper Address (MMUA) MSI Message Data (MMD) PCI Express Identifiers (PXID) PCI Express Capabilities (PXC) Device Capabilities (DEVCAP) Device Control (DEVC) Device Status (DEVS) Vendor Specific Capability Identifiers (VSCID) Vendor Specific Extended Capability Identifiers (VSECID) Device Idle Pointer (DEVIDLEPTR) Device Idle Power On Latency (DEVIDLEPOL) Power Control Enable (PCE)
Vendor Identification (VID)
Device Identification (DID)
Command Register (CMD)
Status Register (STS)
Revision Identification (RID)
Programming Interface (PI)
Sub Class Code (SCC)
Base Class Code (BCC)
Cache Line Size (CLS)
Latency Timer (LT)
Header Type (HTYPE)
Built-in Self Test (BIST)
Intel HD Audio Lower Base Address (HDALBA)
Intel HD Audio Upper Base Address (HDAUBA)
Shadowed PCI Configuration Lower Base Address (SPCLBA)
Shadowed PCI Configuration Upper Base Address (SPCUBA)
DSP Subsystem Lower Base Address (DSPLBA)
DSP Subsystem Upper Base Address (DSPUBA)
Subsystem Vendor Identifier (SVID)
Subsystem Identifier (SID)
Capabilities Pointer (CAPPTR)
Interrupt Line (INTLN)
Interrupt Pin (INTPN)
Power Management Identifiers (PID)
Power Management Capabilities (PC)
Power Management Control & Status (PCS)
MSI Identifiers (MID)
MSI Message Control (MMC)
MSI Message Lower Address (MMLA)
MSI Message Upper Address (MMUA)
MSI Message Data (MMD)
PCI Express Identifiers (PXID)
PCI Express Capabilities (PXC)
Device Capabilities (DEVCAP)
Device Control (DEVC)
Device Status (DEVS)
Vendor Specific Capability Identifiers (VSCID)
Vendor Specific Extended Capability Identifiers (VSECID)
Device Idle Pointer (DEVIDLEPTR)
Device Idle Power On Latency (DEVIDLEPOL)
Power Control Enable (PCE)
Intergrated GbE MMIO
Intergrated GbE MMIO GbE Capabilities and Status Offset 0 (CTRL) GbE Capabilities and Status Offset 18 (CTRL_EXT) GbE Capabilities and Status Offset 20 (MDIC) GbE Capabilities and Status Offset F00 (EXTCNF_CTRL) GbE Capabilities and Status Offset F10 (PHY_CTRL) GbE Capabilities and Status Offset 5400 (RAL_0) GbE Capabilities and Status Offset 5404 (RAH_0) GbE Capabilities and Status Offset 5800 (WUC) GbE Capabilities and Status Offset 5B54 (FWSM)
GbE Capabilities and Status Offset 0 (CTRL)
GbE Capabilities and Status Offset 18 (CTRL_EXT)
GbE Capabilities and Status Offset 20 (MDIC)
GbE Capabilities and Status Offset F00 (EXTCNF_CTRL)
GbE Capabilities and Status Offset F10 (PHY_CTRL)
GbE Capabilities and Status Offset 5400 (RAL_0)
GbE Capabilities and Status Offset 5404 (RAH_0)
GbE Capabilities and Status Offset 5800 (WUC)
GbE Capabilities and Status Offset 5B54 (FWSM)
Keyboard and Text (KT) PCI Configuration
Keyboard and Text (KT) PCI Configuration Device ID And Vendor ID (KT_HOST_DID_VID) Status And Command (KT_HOST_STS_CMD) Class Code And Revision ID (KT_HOST_CC_RID) BIST, Header Type, Latency Timer, And Cache Line Size (KT_HOST_BIST_HTYPE_LT_CLS) KT IO BAR (KT_HOST_IOBAR) KT Memory BAR (KT_HOST_MEMBAR) Cardbus CIS Pointer (KT_HOST_CCP) Subsystem ID And Subsystem Vendor ID (KT_HOST_SID_SVID) Expansion ROM Base Address (KT_HOST_XRBAR) Capabilities List Pointer (KT_HOST_CAPP) Maximum Latency, Minimum Grant, Interrupt Pin And Interrupt Line (KT_HOST_MAXL_MING_INTP_INTL) MSI Message Control, Next Pointer And Capability ID (KT_HOST_MSIMC_MSINP_MSICID) MSI Message Address (KT_HOST_MSIMA) MSI Message Upper Address (KT_HOST_MSIMUA) MSI Message Data (KT_HOST_MSIMD) Power Management Capabilities, Next Pointer And Capability ID (KT_HOST_PMCAP_PMNP_PMCID) Power Management Data, Control/Status Register Bridge Support Extensions, Control And Status (KT_HOST_PMD_PMCSRBSE_PMCSR)
Device ID And Vendor ID (KT_HOST_DID_VID)
Status And Command (KT_HOST_STS_CMD)
Class Code And Revision ID (KT_HOST_CC_RID)
BIST, Header Type, Latency Timer, And Cache Line Size (KT_HOST_BIST_HTYPE_LT_CLS)
KT IO BAR (KT_HOST_IOBAR)
KT Memory BAR (KT_HOST_MEMBAR)
Cardbus CIS Pointer (KT_HOST_CCP)
Subsystem ID And Subsystem Vendor ID (KT_HOST_SID_SVID)
Expansion ROM Base Address (KT_HOST_XRBAR)
Capabilities List Pointer (KT_HOST_CAPP)
Maximum Latency, Minimum Grant, Interrupt Pin And Interrupt Line (KT_HOST_MAXL_MING_INTP_INTL)
MSI Message Control, Next Pointer And Capability ID (KT_HOST_MSIMC_MSINP_MSICID)
MSI Message Address (KT_HOST_MSIMA)
MSI Message Upper Address (KT_HOST_MSIMUA)
MSI Message Data (KT_HOST_MSIMD)
Power Management Capabilities, Next Pointer And Capability ID (KT_HOST_PMCAP_PMNP_PMCID)
Power Management Data, Control/Status Register Bridge Support Extensions, Control And Status (KT_HOST_PMD_PMCSRBSE_PMCSR)
P2SB PCI Configuration
P2SB PCI Configuration PCI Identifier (PCIID) PCI Command (PCICMD) Revision ID (PCIRID_CC) PCI Header Type (PCIHTYPE) Sideband Register Access BAR (SBREG_BAR) Sideband Register BAR High DWORD (SBREG_BARH) Routing Configuration (RCFG) High Performance Event Timer Configuration (HPTC) IOxAPIC Configuration (IOAC) HPET Bus:Device:Function (HBDF) Display Bus:Device:Function (DISPBDF)
PCI Identifier (PCIID)
PCI Command (PCICMD)
Revision ID (PCIRID_CC)
PCI Header Type (PCIHTYPE)
Sideband Register Access BAR (SBREG_BAR)
Sideband Register BAR High DWORD (SBREG_BARH)
Routing Configuration (RCFG)
High Performance Event Timer Configuration (HPTC)
IOxAPIC Configuration (IOAC)
HPET Bus:Device:Function (HBDF)
Display Bus:Device:Function (DISPBDF)
PCIe* PCI Configuration
PCIe* PCI Configuration Identifiers (ID) Device Command (CMD) Primary Status (PSTS) Revision ID (RID_CC) Cache Line Size (CLS) Header Type (HTYPE) Base Address Register 0 (BAR0) Base Address Register 1 (BAR1) Bus Numbers (BNUM_SLT) I/O Base And Limit (IOBL) Secondary Status (SSTS) Memory Base And Limit (MBL) Prefetchable Memory Base And Limit (PMBL) Prefetchable Memory Base Upper 32 Bits (PMBU32) Prefetchable Memory Limit Upper 32 Bits (PMLU32) Capabilities List Pointer (CAPP) Interrupt Information Byte 0 (INTRB0) Interrupt Information Byte 1 (INTRB1) Bridge Control (BCTRL) Capabilities List (CLIST) PCI Express Capabilities (XCAP) Device Capabilities (DCAP) Device Control (DCTL) Device Status (DSTS) Link Capabilities (LCAP) Link Control (LCTL) Link Status (LSTS) Slot Capabilities (SLCAP) Slot Control (SLCTL) Slot Status (SLSTS) Root Control (RCTL) Root Capabilities (ROOTCAP) Root Status (RSTS) Device Capabilities 2 (DCAP2) Device Control 2 (DCTL2) Link Capabilities 2 (LCAP2) Link Control 2 (LCTL2) Link Status 2 (LSTS2) Message Signaled Interrupt Identifiers (MID) Message Signaled Interrupt Message (MC) Message Signaled Interrupt Message Address (MA) Message Signaled Interrupt Message Upper Address (MUA) Message Signaled Interrupt Message Data (MD) Subsystem Vendor Capability (SVCAP) Subsystem Vendor IDs (SVID) Power Management Capability (PMCAP) PCI Power Management Capabilities (PMC) PCI Power Management Control (PMCS) Advanced Error Extended (AECH) Uncorrectable Error Status (UES) Uncorrectable Error Mask (UEM) Uncorrectable Error Severity (UEV) Correctable Error Status (CES) Correctable Error Mask (CEM) Advanced Error Capabilities And Control (AECC) Root Error Command (REC) Root Error Status (RES) Error Source Identification (ESID) PTM Extended Capability Header (PTMECH) PTM Capability Register (PTMCAPR) PTM Control Register (PTMCTLR) L1 Sub-States Extended Capability Header (L1SECH) L1 Sub-States Capabilities (L1SCAP) L1 Sub-States Control 1 (L1SCTL1) L1 Sub-States Control 2 (L1SCTL2) ACS Extended Capability Header (ACSECH) ACS Capability Register (ACSCAPR) ACS Control Register (ACSCTLR) Port VC Capability Register 1 (PVCCR1) Port VC Capability 2 (PVCC2) Port VC Control (PVCC) Port VC Status (PVCS) Virtual Channel 0 Resource Capability (V0VCRC) Virtual Channel 0 Resource Control (V0CTL) Virtual Channel 0 Resource Status (V0STS) Virtual Channel 1 Resource Capability (V1VCRC) Virtual Channel 1 Resource Control (V1CTL) Virtual Channel 1 Resource Status (V1STS) DPC Extended Capability Header (DPCECH) DPC Capability Register (DPCCAPR) DPC Control Register (DPCCTLR) DPC Status Register (DPCSR) DPC Error Source ID Register (DPCESIDR) RP PIO Status Register (RPPIOSR) RP PIO Mask Register (RPPIOMR) RP PIO Severity Register (RPPIOVR) RP PIO SysError Register (RPPIOSER) RP PIO Exception Register (RPPIOER) RP PIO Header Log DW1 Register (RPPIOHLR_DW1) RP PIO Header Log DW2 Register (RPPIOHLR_DW2) RP PIO Header Log DW3 Register (RPPIOHLR_DW3) RP PIO Header Log DW4 Register (RPPIOHLR_DW4) Secondary PCI Express Extended Capability Header (SPEECH) Link Control 3 (LCTL3) Lane Error Status (LES) Lane 0 And Lane 1 Equalization Control (L01EC) Lane 2 And Lane 3 Equalization Control (L23EC) Lane 4 And Lane 5 Equalization Control (L45EC) Lane 6 And Lane 7 Equalization Control (L67EC) Lane 8 And Lane 9 Equalization Control (L89EC) Lane 10 And Lane 11 Equalization Control (L1011EC) Lane 12 And Lane 13 Equalization Control (L1213EC) Lane 14 And Lane 15 Equalization Control (L1415EC) Data Link Feature Extended Capability Header (DLFECH) Data Link Feature Capabilities Register (DLFCAP) Data Link Feature Status Register (DLFSTS) Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH) Physical Layer 16.0 GT/s Status Register (PL16S) Physical Layer 16.0 GT/s Local Data Parity Mismatch Status Register (PL16LDPMS) Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS) Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS) Physical Layer 16.0 GT/s Lane 01 Equalization Control Register (PL16L01EC) Physical Layer 16.0 GT/s Lane 23 Equalization Control Register (PL16L23EC) Physical Layer 16.0 GT/s Lane 45 Equalization Control Register (PL16L45EC) Physical Layer 16.0 GT/s Lane 67 Equalization Control Register (PL16L67EC) Physical Layer 16.0 GT/s Lane 89 Equalization Control Register (PL16L89EC) Physical Layer 16.0 GT/s Lane 1011 Equalization Control Register (PL16L1011EC) Physical Layer 16.0 GT/s Lane 1213 Equalization Control Register (PL16L1213EC) Physical Layer 16.0 GT/s Lane 1415 Equalization Control Register (PL16L1415EC) Physical Layer 32.0 GT/s Extended Capability Header (G5ECH) Physical Layer 32.0 GT/s Capability Register (G5CAP) Physical Layer 32.0 GT/s Control Register (G5CTL) Physical Layer 32.0 GT/s Status Register (G5STS) Receiver Modified TS Data 1 Register (RCVDMODTSDATA1) Receiver Modified TS Data 2 Register (RCVDMODTSDATA2) Transmitted Modified TS Data 1 Register (TRNSMODTSDATA1) Transmitted Modified TS Data 2 Register (TRNSMODTSDATA2) Alternate Protocol Extended Capability Header (APEC) Alternate Protocol Capabilities Register (APCAPR) Alternate Protocol Control Register (APCTRLR) Alternate Protocol Data 1 Register (APD1R) Alternate Protocol Data 2 Register (APD2R) Alternate Protocol Selective Enable Mask Register (APSEMR) Multicast Extended Capability Header (MCECH) Multicast Extended Capability Register (MCAPR) Multicast Control Register (MCCTLR) Multicast Base Address Register 1 (MCBADRR1) Multicast Base Address Register 2 (MCBADRR2) Multicast Receive Register (MCRR) Multicast Block All Register (MCBAR) Multicast Block Untranslated Register (MCBUR) Multicast Overlay BAR 1 (MCOB1) Multicast Overlay BAR 2 (MCOB2) VNN Removal Control (VNNREMCTL) VNN Removal Save And Restore Hardware Contexts 1 (VNNRSNRC1) Physical Layer 16.0 GT/s Margining Extended Capability Header (PL16MECH) Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status Byte 0 & 1 (PL16MPCPSB01) Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status Byte 2 & 3 (PL16MPCPSB23) Physical Layer 16.0 GT/s Lane0 Margin Control and Status Register (PL16L0MCS) Physical Layer 16.0 GT/s Lane1 Margin Control and Status Register (PL16L1MCS) Physical Layer 16.0 GT/s Lane2 Margin Control and Status Register (PL16L2MCS) Physical Layer 16.0 GT/s Lane3 Margin Control and Status Register (PL16L3MCS) Physical Layer 16.0 GT/s Lane4 Margin Control and Status Register (PL16L4MCS) Physical Layer 16.0 GT/s Lane5 Margin Control and Status Register (PL16L5MCS) Physical Layer 16.0 GT/s Lane6 Margin Control and Status Register (PL16L6MCS) Physical Layer 16.0 GT/s Lane7 Margin Control and Status Register (PL16L7MCS) Physical Layer 16.0 GT/s Lane8 Margin Control and Status Register (PL16L8MCS) Physical Layer 16.0 GT/s Lane9 Margin Control and Status Register (PL16L9MCS) Physical Layer 16.0 GT/s Lane10 Margin Control and Status Register (PL16L10MCS) Physical Layer 16.0 GT/s Lane11 Margin Control and Status Register (PL16L11MCS) Physical Layer 16.0 GT/s Lane12 Margin Control and Status Register (PL16L12MCS) Physical Layer 16.0 GT/s Lane13 Margin Control and Status Register (PL16L13MCS) Physical Layer 16.0 GT/s Lane14 Margin Control and Status Register (PL16L14MCS) Physical Layer 16.0 GT/s Lane15 Margin Control and Status Register (PL16L15MCS)
Identifiers (ID)
Device Command (CMD)
Primary Status (PSTS)
Revision ID (RID_CC)
Cache Line Size (CLS)
Header Type (HTYPE)
Base Address Register 0 (BAR0)
Base Address Register 1 (BAR1)
Bus Numbers (BNUM_SLT)
I/O Base And Limit (IOBL)
Secondary Status (SSTS)
Memory Base And Limit (MBL)
Prefetchable Memory Base And Limit (PMBL)
Prefetchable Memory Base Upper 32 Bits (PMBU32)
Prefetchable Memory Limit Upper 32 Bits (PMLU32)
Capabilities List Pointer (CAPP)
Interrupt Information Byte 0 (INTRB0)
Interrupt Information Byte 1 (INTRB1)
Bridge Control (BCTRL)
Capabilities List (CLIST)
PCI Express Capabilities (XCAP)
Device Capabilities (DCAP)
Device Control (DCTL)
Device Status (DSTS)
Link Capabilities (LCAP)
Link Control (LCTL)
Link Status (LSTS)
Slot Capabilities (SLCAP)
Slot Control (SLCTL)
Slot Status (SLSTS)
Root Control (RCTL)
Root Capabilities (ROOTCAP)
Root Status (RSTS)
Device Capabilities 2 (DCAP2)
Device Control 2 (DCTL2)
Link Capabilities 2 (LCAP2)
Link Control 2 (LCTL2)
Link Status 2 (LSTS2)
Message Signaled Interrupt Identifiers (MID)
Message Signaled Interrupt Message (MC)
Message Signaled Interrupt Message Address (MA)
Message Signaled Interrupt Message Upper Address (MUA)
Message Signaled Interrupt Message Data (MD)
Subsystem Vendor Capability (SVCAP)
Subsystem Vendor IDs (SVID)
Power Management Capability (PMCAP)
PCI Power Management Capabilities (PMC)
PCI Power Management Control (PMCS)
Advanced Error Extended (AECH)
Uncorrectable Error Status (UES)
Uncorrectable Error Mask (UEM)
Uncorrectable Error Severity (UEV)
Correctable Error Status (CES)
Correctable Error Mask (CEM)
Advanced Error Capabilities And Control (AECC)
Root Error Command (REC)
Root Error Status (RES)
Error Source Identification (ESID)
PTM Extended Capability Header (PTMECH)
PTM Capability Register (PTMCAPR)
PTM Control Register (PTMCTLR)
L1 Sub-States Extended Capability Header (L1SECH)
L1 Sub-States Capabilities (L1SCAP)
L1 Sub-States Control 1 (L1SCTL1)
L1 Sub-States Control 2 (L1SCTL2)
ACS Extended Capability Header (ACSECH)
ACS Capability Register (ACSCAPR)
ACS Control Register (ACSCTLR)
Port VC Capability Register 1 (PVCCR1)
Port VC Capability 2 (PVCC2)
Port VC Control (PVCC)
Port VC Status (PVCS)
Virtual Channel 0 Resource Capability (V0VCRC)
Virtual Channel 0 Resource Control (V0CTL)
Virtual Channel 0 Resource Status (V0STS)
Virtual Channel 1 Resource Capability (V1VCRC)
Virtual Channel 1 Resource Control (V1CTL)
Virtual Channel 1 Resource Status (V1STS)
DPC Extended Capability Header (DPCECH)
DPC Capability Register (DPCCAPR)
DPC Control Register (DPCCTLR)
DPC Status Register (DPCSR)
DPC Error Source ID Register (DPCESIDR)
RP PIO Status Register (RPPIOSR)
RP PIO Mask Register (RPPIOMR)
RP PIO Severity Register (RPPIOVR)
RP PIO SysError Register (RPPIOSER)
RP PIO Exception Register (RPPIOER)
RP PIO Header Log DW1 Register (RPPIOHLR_DW1)
RP PIO Header Log DW2 Register (RPPIOHLR_DW2)
RP PIO Header Log DW3 Register (RPPIOHLR_DW3)
RP PIO Header Log DW4 Register (RPPIOHLR_DW4)
Secondary PCI Express Extended Capability Header (SPEECH)
Link Control 3 (LCTL3)
Lane Error Status (LES)
Lane 0 And Lane 1 Equalization Control (L01EC)
Lane 2 And Lane 3 Equalization Control (L23EC)
Lane 4 And Lane 5 Equalization Control (L45EC)
Lane 6 And Lane 7 Equalization Control (L67EC)
Lane 8 And Lane 9 Equalization Control (L89EC)
Lane 10 And Lane 11 Equalization Control (L1011EC)
Lane 12 And Lane 13 Equalization Control (L1213EC)
Lane 14 And Lane 15 Equalization Control (L1415EC)
Data Link Feature Extended Capability Header (DLFECH)
Data Link Feature Capabilities Register (DLFCAP)
Data Link Feature Status Register (DLFSTS)
Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH)
Physical Layer 16.0 GT/s Status Register (PL16S)
Physical Layer 16.0 GT/s Local Data Parity Mismatch Status Register (PL16LDPMS)
Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS)
Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS)
Physical Layer 16.0 GT/s Lane 01 Equalization Control Register (PL16L01EC)
Physical Layer 16.0 GT/s Lane 23 Equalization Control Register (PL16L23EC)
Physical Layer 16.0 GT/s Lane 45 Equalization Control Register (PL16L45EC)
Physical Layer 16.0 GT/s Lane 67 Equalization Control Register (PL16L67EC)
Physical Layer 16.0 GT/s Lane 89 Equalization Control Register (PL16L89EC)
Physical Layer 16.0 GT/s Lane 1011 Equalization Control Register (PL16L1011EC)
Physical Layer 16.0 GT/s Lane 1213 Equalization Control Register (PL16L1213EC)
Physical Layer 16.0 GT/s Lane 1415 Equalization Control Register (PL16L1415EC)
Physical Layer 32.0 GT/s Extended Capability Header (G5ECH)
Physical Layer 32.0 GT/s Capability Register (G5CAP)
Physical Layer 32.0 GT/s Control Register (G5CTL)
Physical Layer 32.0 GT/s Status Register (G5STS)
Receiver Modified TS Data 1 Register (RCVDMODTSDATA1)
Receiver Modified TS Data 2 Register (RCVDMODTSDATA2)
Transmitted Modified TS Data 1 Register (TRNSMODTSDATA1)
Transmitted Modified TS Data 2 Register (TRNSMODTSDATA2)
Alternate Protocol Extended Capability Header (APEC)
Alternate Protocol Capabilities Register (APCAPR)
Alternate Protocol Control Register (APCTRLR)
Alternate Protocol Data 1 Register (APD1R)
Alternate Protocol Data 2 Register (APD2R)
Alternate Protocol Selective Enable Mask Register (APSEMR)
Multicast Extended Capability Header (MCECH)
Multicast Extended Capability Register (MCAPR)
Multicast Control Register (MCCTLR)
Multicast Base Address Register 1 (MCBADRR1)
Multicast Base Address Register 2 (MCBADRR2)
Multicast Receive Register (MCRR)
Multicast Block All Register (MCBAR)
Multicast Block Untranslated Register (MCBUR)
Multicast Overlay BAR 1 (MCOB1)
Multicast Overlay BAR 2 (MCOB2)
VNN Removal Control (VNNREMCTL)
VNN Removal Save And Restore Hardware Contexts 1 (VNNRSNRC1)
Physical Layer 16.0 GT/s Margining Extended Capability Header (PL16MECH)
Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status Byte 0 & 1 (PL16MPCPSB01)
Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status Byte 2 & 3 (PL16MPCPSB23)
Physical Layer 16.0 GT/s Lane0 Margin Control and Status Register (PL16L0MCS)
Physical Layer 16.0 GT/s Lane1 Margin Control and Status Register (PL16L1MCS)
Physical Layer 16.0 GT/s Lane2 Margin Control and Status Register (PL16L2MCS)
Physical Layer 16.0 GT/s Lane3 Margin Control and Status Register (PL16L3MCS)
Physical Layer 16.0 GT/s Lane4 Margin Control and Status Register (PL16L4MCS)
Physical Layer 16.0 GT/s Lane5 Margin Control and Status Register (PL16L5MCS)
Physical Layer 16.0 GT/s Lane6 Margin Control and Status Register (PL16L6MCS)
Physical Layer 16.0 GT/s Lane7 Margin Control and Status Register (PL16L7MCS)
Physical Layer 16.0 GT/s Lane8 Margin Control and Status Register (PL16L8MCS)
Physical Layer 16.0 GT/s Lane9 Margin Control and Status Register (PL16L9MCS)
Physical Layer 16.0 GT/s Lane10 Margin Control and Status Register (PL16L10MCS)
Physical Layer 16.0 GT/s Lane11 Margin Control and Status Register (PL16L11MCS)
Physical Layer 16.0 GT/s Lane12 Margin Control and Status Register (PL16L12MCS)
Physical Layer 16.0 GT/s Lane13 Margin Control and Status Register (PL16L13MCS)
Physical Layer 16.0 GT/s Lane14 Margin Control and Status Register (PL16L14MCS)
Physical Layer 16.0 GT/s Lane15 Margin Control and Status Register (PL16L15MCS)
PMC I/O Based
PMC I/O Based Power Management 1 Enables and Status (PM1_EN_STS) Power Management 1 Control (PM1_CNT) Power Management 1 Timer (PM1_TMR) General Purpose Event 1 Status [31:0] (GPE1_STS_31_0) General Purpose Event 1 Status [63:32] (GPE1_STS_63_32) General Purpose Event 1 Status [63:32] (GPE1_STS_95_64) General Purpose Event 1 Enable [31:0] (GPE1_EN_31_0) General Purpose Event 1 Enable [63:32] (GPE1_EN_63_32) General Purpose Event 1 Enable [63:32] (GPE1_EN_95_64) SMI Control and Enable (SMI_EN) SMI Status Register (SMI_STS) General Purpose Event Control (GPE_CTRL) Device Trap Status Register (DEVTRAP_STS) Therm Timer Delay Register (THERM_TIMER_DELAY) PM2a Control Block (PM2A_CNT_BLK) Over-Clocking WDT Control (OC_WDT_CTL) General Purpose Event 0 Status [31:0] (GPE0_STS_31_0) General Purpose Event 0 Status [63:32] (GPE0_STS_63_32) General Purpose Event 0 Status [95:64] (GPE0_STS_95_64) General Purpose Event 0 Status [127:96] (GPE0_STS_127_96) General Purpose Event 0 Enable [31:0] (GPE0_EN_31_0) General Purpose Event 0 Enable [63:32] (GPE0_EN_63_32) General Purpose Event 0 Enable [95:64] (GPE0_EN_95_64) General Purpose Event 0 Enable [127:96] (GPE0_EN_127_96)
Power Management 1 Enables and Status (PM1_EN_STS)
Power Management 1 Control (PM1_CNT)
Power Management 1 Timer (PM1_TMR)
General Purpose Event 1 Status [31:0] (GPE1_STS_31_0)
General Purpose Event 1 Status [63:32] (GPE1_STS_63_32)
General Purpose Event 1 Status [63:32] (GPE1_STS_95_64)
General Purpose Event 1 Enable [31:0] (GPE1_EN_31_0)
General Purpose Event 1 Enable [63:32] (GPE1_EN_63_32)
General Purpose Event 1 Enable [63:32] (GPE1_EN_95_64)
SMI Control and Enable (SMI_EN)
SMI Status Register (SMI_STS)
General Purpose Event Control (GPE_CTRL)
Device Trap Status Register (DEVTRAP_STS)
Therm Timer Delay Register (THERM_TIMER_DELAY)
PM2a Control Block (PM2A_CNT_BLK)
Over-Clocking WDT Control (OC_WDT_CTL)
General Purpose Event 0 Status [31:0] (GPE0_STS_31_0)
General Purpose Event 0 Status [63:32] (GPE0_STS_63_32)
General Purpose Event 0 Status [95:64] (GPE0_STS_95_64)
General Purpose Event 0 Status [127:96] (GPE0_STS_127_96)
General Purpose Event 0 Enable [31:0] (GPE0_EN_31_0)
General Purpose Event 0 Enable [63:32] (GPE0_EN_63_32)
General Purpose Event 0 Enable [95:64] (GPE0_EN_95_64)
General Purpose Event 0 Enable [127:96] (GPE0_EN_127_96)
PMC MMIO
PMC MMIO General PM Configuration A (GEN_PMCON_A) General PM Configuration B (GEN_PMCON_B) Configured Revision ID (CRID) Extended Test Mode Register 3 (ETR3) SET STRAP MSG LOCK (SSML) SET STRAP MSG CONTROL (SSMC) SET STRAP MSG DATA (SSMD) Configured Revision ID (CRID_UIP) SLP S0 DEBUG REG0 (SLP_S0_DBG_0) SLP S0 DEBUG REG1 (SLP_S0_DBG_1) SLP S0 DEBUG REG2 (SLP_S0_DBG_2) HSIO Power Management Configuration Reg 1 (MODPHY_PM_CFG1) HSIO Power Management Configuration Reg 2 (MODPHY_PM_CFG2) HSIO Power Management Configuration Reg 3 (MODPHY_PM_CFG3) HSIO Power Management Configuration Reg 4 (MODPHY_PM_CFG4) HSIO Power Management Configuration Reg 5 (MODPHY_PM_CFG5) HSIO Power Management Configuration Reg 6 (MODPHY_PM_CFG6) EXT FET RAMP CFG (EXT_FET_RAMP_CFG) VCCIN AUX CONFIG Register (VCCIN_AUX_CFG) Always Running Timer Value 31:0 (ARTV_31_0) Always Running Timer Value 31:0 (ARTV_63_32) Always Running Timer Value Control (ARTV_CTRL) Timed GPIO Control 0 (TGPIOCTL0) Timed GPIO 0 Comparator Value 31:0 (TGPIOCOMPV0_31_0) Timed GPIO Comparator Value 63:32 (TGPIOCOMPV0_63_32) Timed GPIO0 Periodic Interval Value 31_0 (TGPIOPIV0_31_0) Timed GPIO 0 Periodic Interval Value 63_32 (TGPIOPIV0_63_32) Timed GPIO Time Capture Register 31_0 (TGPIOTCV0_31_0) Timed GPIO0 Time Capture Register 63_32 (TGPIOTCV0_63_32) Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV0_31_0) Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV0_63_32) Timed GPIO0 Event Counter Register 31_0 (TGPIOEC0_31_0) Timed GPIO0 Event Counter Register 63_32 (TGPIOEC0_63_32) Timed GPIO Control 1 (TGPIOCTL1) Timed GPIO 1 Comparator Value 31:0 (TGPIOCOMPV1_31_0) Timed GPIO Comparator Value 63:32 (TGPIOCOMPV1_63_32) Timed GPIO1 Periodic Interval Value 31_0 (TGPIOPIV1_31_0) Timed GPIO 1 Periodic Interval Value 63_32 (TGPIOPIV1_63_32) Timed GPIO Time Capture Register 31_0 (TGPIOTCV1_31_0) Timed GPIO Time Capture Register 63_32 (TGPIOTCV1_63_32) Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV1_31_0) Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV1_63_32) Timed GPIO1 Event Counter Register 31_0 (TGPIOEC1_31_0) Timed GPIO Event Counter Register 63_32 (TGPIOEC1_63_32) Min Temperature (MIN_TEMP) Max Temperature (MAX_TEMP) Catastrophic Trip Point Enable (CTEN) EC Thermal Sensor Reporting Enable (ECRPTEN) Throttle Level (TL) SW Throttle (SWTHROT) Throttle Levels Enable (TLEN) Thermal Sensor Alert High Value (TSAHV) Thermal Sensor Alert Low Value (TSALV) Thermal Alert Trip Status (TAS) PCH Hot Level Control (PHLC) Temperature Sensor Control and Status (TSS0) SoC-to-IOE Force Thermal Throttling Control (S2I_FTT_CTRL) Wake Alarm Device Timer: AC (WADT_AC) Wake Alarm Device Timer: DC (WADT_DC) Wake Alarm Device Expired Timer: AC (WADT_EXP_AC) Wake Alarm Device Expired Timer: DC (WADT_EXP_DC) Power and Reset Status (PRSTS) Power Management Configuration Reg 1 (PM_CFG) S3 Power Gating Policies (S3_PWRGATE_POL) S4 Power Gating Policies (S4_PWRGATE_POL) S5 Power Gating Policies (S5_PWRGATE_POL) DeepSx Configuration (DSX_CFG) Power Management Configuration Reg 2 (PM_CFG2) Power Management Configuration Reg 3 (PM_CFG3) Power Management Configuration Reg 4 (PM_CFG4) CPU Early Power-on Configuration (CPU_EPOC) ADR Enable (ADR_EN) ACPI Timer Control (ACPI_TMR_CTL) ADR General Configuration (ADR_GEN_CFG) Last TSC Alarm Value[31:0] (TSC_ALARM_LO) Last TSC Alarm Value[63:32] (TSC_ALARM_HI) GPIO Configuration (GPIO_CFG) Host Partition Reset Causes (HPR_CAUSE0) Latency Limit Residency 0 (LAT_LIM_RES_0) Latency Limit Residency 1 (LAT_LIM_RES_1) Latency Limit Residency 2 (LAT_LIM_RES_2) SLP_S0 Residency (SLP_S0_RESIDENCY) Latency Limit Control (LATENCY_LIMIT_CONTROL) ADR Control and Status (ADR_CTRL_STS) ACPI Control (ACTL) S0 Residency (S0_RES) PGD PG_ACK Status Register 0 (PPASR0) PGD PG_ACK Status Register 1 (PPASR1) PGD PFET Enable Ack Status Register 0 (PPFEAR0) PGD PFET Enable Ack Status Register 1 (PPFEAR1) PGD PG_REQ Status Register 0 (PPRSR0) PGD PG_REQ Status Register 1 (PPRSR1) ST_PG_FDIS_PMC - Register 1 (ST_PG_FDIS_PMC_1) ST_PG_FDIS_PMC - Register 2 (ST_PG_FDIS_PMC_2)
General PM Configuration A (GEN_PMCON_A)
General PM Configuration B (GEN_PMCON_B)
Configured Revision ID (CRID)
Extended Test Mode Register 3 (ETR3)
SET STRAP MSG LOCK (SSML)
SET STRAP MSG CONTROL (SSMC)
SET STRAP MSG DATA (SSMD)
Configured Revision ID (CRID_UIP)
SLP S0 DEBUG REG0 (SLP_S0_DBG_0)
SLP S0 DEBUG REG1 (SLP_S0_DBG_1)
SLP S0 DEBUG REG2 (SLP_S0_DBG_2)
HSIO Power Management Configuration Reg 1 (MODPHY_PM_CFG1)
HSIO Power Management Configuration Reg 2 (MODPHY_PM_CFG2)
HSIO Power Management Configuration Reg 3 (MODPHY_PM_CFG3)
HSIO Power Management Configuration Reg 4 (MODPHY_PM_CFG4)
HSIO Power Management Configuration Reg 5 (MODPHY_PM_CFG5)
HSIO Power Management Configuration Reg 6 (MODPHY_PM_CFG6)
EXT FET RAMP CFG (EXT_FET_RAMP_CFG)
VCCIN AUX CONFIG Register (VCCIN_AUX_CFG)
Always Running Timer Value 31:0 (ARTV_31_0)
Always Running Timer Value 31:0 (ARTV_63_32)
Always Running Timer Value Control (ARTV_CTRL)
Timed GPIO Control 0 (TGPIOCTL0)
Timed GPIO 0 Comparator Value 31:0 (TGPIOCOMPV0_31_0)
Timed GPIO Comparator Value 63:32 (TGPIOCOMPV0_63_32)
Timed GPIO0 Periodic Interval Value 31_0 (TGPIOPIV0_31_0)
Timed GPIO 0 Periodic Interval Value 63_32 (TGPIOPIV0_63_32)
Timed GPIO Time Capture Register 31_0 (TGPIOTCV0_31_0)
Timed GPIO0 Time Capture Register 63_32 (TGPIOTCV0_63_32)
Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV0_31_0)
Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV0_63_32)
Timed GPIO0 Event Counter Register 31_0 (TGPIOEC0_31_0)
Timed GPIO0 Event Counter Register 63_32 (TGPIOEC0_63_32)
Timed GPIO Control 1 (TGPIOCTL1)
Timed GPIO 1 Comparator Value 31:0 (TGPIOCOMPV1_31_0)
Timed GPIO Comparator Value 63:32 (TGPIOCOMPV1_63_32)
Timed GPIO1 Periodic Interval Value 31_0 (TGPIOPIV1_31_0)
Timed GPIO 1 Periodic Interval Value 63_32 (TGPIOPIV1_63_32)
Timed GPIO Time Capture Register 31_0 (TGPIOTCV1_31_0)
Timed GPIO Time Capture Register 63_32 (TGPIOTCV1_63_32)
Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV1_31_0)
Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV1_63_32)
Timed GPIO1 Event Counter Register 31_0 (TGPIOEC1_31_0)
Timed GPIO Event Counter Register 63_32 (TGPIOEC1_63_32)
Min Temperature (MIN_TEMP)
Max Temperature (MAX_TEMP)
Catastrophic Trip Point Enable (CTEN)
EC Thermal Sensor Reporting Enable (ECRPTEN)
Throttle Level (TL)
SW Throttle (SWTHROT)
Throttle Levels Enable (TLEN)
Thermal Sensor Alert High Value (TSAHV)
Thermal Sensor Alert Low Value (TSALV)
Thermal Alert Trip Status (TAS)
PCH Hot Level Control (PHLC)
Temperature Sensor Control and Status (TSS0)
SoC-to-IOE Force Thermal Throttling Control (S2I_FTT_CTRL)
Wake Alarm Device Timer: AC (WADT_AC)
Wake Alarm Device Timer: DC (WADT_DC)
Wake Alarm Device Expired Timer: AC (WADT_EXP_AC)
Wake Alarm Device Expired Timer: DC (WADT_EXP_DC)
Power and Reset Status (PRSTS)
Power Management Configuration Reg 1 (PM_CFG)
S3 Power Gating Policies (S3_PWRGATE_POL)
S4 Power Gating Policies (S4_PWRGATE_POL)
S5 Power Gating Policies (S5_PWRGATE_POL)
DeepSx Configuration (DSX_CFG)
Power Management Configuration Reg 2 (PM_CFG2)
Power Management Configuration Reg 3 (PM_CFG3)
Power Management Configuration Reg 4 (PM_CFG4)
CPU Early Power-on Configuration (CPU_EPOC)
ADR Enable (ADR_EN)
ACPI Timer Control (ACPI_TMR_CTL)
ADR General Configuration (ADR_GEN_CFG)
Last TSC Alarm Value[31:0] (TSC_ALARM_LO)
Last TSC Alarm Value[63:32] (TSC_ALARM_HI)
GPIO Configuration (GPIO_CFG)
Host Partition Reset Causes (HPR_CAUSE0)
Latency Limit Residency 0 (LAT_LIM_RES_0)
Latency Limit Residency 1 (LAT_LIM_RES_1)
Latency Limit Residency 2 (LAT_LIM_RES_2)
SLP_S0 Residency (SLP_S0_RESIDENCY)
Latency Limit Control (LATENCY_LIMIT_CONTROL)
ADR Control and Status (ADR_CTRL_STS)
ACPI Control (ACTL)
S0 Residency (S0_RES)
PGD PG_ACK Status Register 0 (PPASR0)
PGD PG_ACK Status Register 1 (PPASR1)
PGD PFET Enable Ack Status Register 0 (PPFEAR0)
PGD PFET Enable Ack Status Register 1 (PPFEAR1)
PGD PG_REQ Status Register 0 (PPRSR0)
PGD PG_REQ Status Register 1 (PPRSR1)
ST_PG_FDIS_PMC - Register 1 (ST_PG_FDIS_PMC_1)
ST_PG_FDIS_PMC - Register 2 (ST_PG_FDIS_PMC_2)
PMC PCI Configuration
PMC PCI Configuration Device Vendor ID (DEVVENDID) Status and Command (STATUSCOMMAND) Revision Class Codes (REVCLASSCODE) Cache Line Latency Header And BIST (CLLATHEADERBIST) Base Address Register (BAR) Base Address Register High (BAR_HIGH) Base Address Register 1 (BAR1) Base Address Register 1 High (BAR1_HIGH) Base Address Register2 (BAR2) Subsystem Identifiers (SUBSYSTEMID) EXPANSION ROM base address (EXPANSION_ROM_BASEADDR) Capabilities Pointer (CAPABILITYPTR) Interrupt Register (INTERRUPTREG) PowerManagement Capability ID (POWERCAPID) Power Management Control and Status (PMECTRLSTATUS) PCI Device Idle Capability Record (PCIDEVIDLE_CAP_RECORD) Device Vendor Specific (DEVID_VEND_SPECIFIC_REG) D0I3 CONTROL SW LTR MMIO REG (D0I3_CONTROL_SW_LTR_MMIO_REG) Device IDLE pointer register (DEVICE_IDLE_POINTER_REG) D0I3 MAX POW LAT PG CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG) General Purpose Read Write Register1 (GEN_REGRW1) General Purpose Read Write Register2 (GEN_REGRW2) General Purpose Read Write Register3 (GEN_REGRW3) General Purpose Read Write Register4 (GEN_REGRW4) General Purpose Input Register (GEN_INPUT_REG)
Device Vendor ID (DEVVENDID)
Status and Command (STATUSCOMMAND)
Revision Class Codes (REVCLASSCODE)
Cache Line Latency Header And BIST (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register 1 (BAR1)
Base Address Register 1 High (BAR1_HIGH)
Base Address Register2 (BAR2)
Subsystem Identifiers (SUBSYSTEMID)
EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
PowerManagement Capability ID (POWERCAPID)
Power Management Control and Status (PMECTRLSTATUS)
PCI Device Idle Capability Record (PCIDEVIDLE_CAP_RECORD)
Device Vendor Specific (DEVID_VEND_SPECIFIC_REG)
D0I3 CONTROL SW LTR MMIO REG (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device IDLE pointer register (DEVICE_IDLE_POINTER_REG)
D0I3 MAX POW LAT PG CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write Register1 (GEN_REGRW1)
General Purpose Read Write Register2 (GEN_REGRW2)
General Purpose Read Write Register3 (GEN_REGRW3)
General Purpose Read Write Register4 (GEN_REGRW4)
General Purpose Input Register (GEN_INPUT_REG)
PMC SSRAM PCI Configuration
PMC SSRAM PCI Configuration Device Vendor ID (DEVVENDID) STATUSCOMMAND Status and Command (STATUSCOMMAND) Revision Class Codes (REVCLASSCODE) CLLATHEADERBIST Cache Line Latency Header And BIST (CLLATHEADERBIST) 32-bit Base Address Register (BAR) BAR HIGH (BAR_HIGH) 32-bit Base Address Register1 (BAR1) BAR1 HIGH (BAR1_HIGH) Subsystem Identifiers (SUBSYSTEMID) EXPANSION ROM BASEADDR (EXPANSION_ROM_BASEADDR) CAPABILITY PTR (CAPABILITYPTR) INTERRUPT REG Interrupt Register (INTERRUPTREG) POWER CAP ID PowerManagement Capability ID (POWERCAPID) PME CTRL STATUS (PMECTRLSTATUS) PCIDEVIDLE CAP RECORD (PCIDEVIDLE_CAP_RECORD) DEVID VEND SPECIFIC REG (DEVID_VEND_SPECIFIC_REG) D0I3 CONTROL SW LTR MMIO REG (D0I3_CONTROL_SW_LTR_MMIO_REG) DEVICE IDLE POINTER REG (DEVICE_IDLE_POINTER_REG) D0I3 MAX POW LAT PG CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG) GEN REG RW1 (GEN_REGRW1) GEN REG RW2 (GEN_REGRW2) GEN REG RW3 (GEN_REGRW3) GEN REG RW4 (GEN_REGRW4) GEN INPUT REG (GEN_INPUT_REG)
Device Vendor ID (DEVVENDID)
STATUSCOMMAND Status and Command (STATUSCOMMAND)
Revision Class Codes (REVCLASSCODE)
CLLATHEADERBIST Cache Line Latency Header And BIST (CLLATHEADERBIST)
32-bit Base Address Register (BAR)
BAR HIGH (BAR_HIGH)
32-bit Base Address Register1 (BAR1)
BAR1 HIGH (BAR1_HIGH)
Subsystem Identifiers (SUBSYSTEMID)
EXPANSION ROM BASEADDR (EXPANSION_ROM_BASEADDR)
CAPABILITY PTR (CAPABILITYPTR)
INTERRUPT REG Interrupt Register (INTERRUPTREG)
POWER CAP ID PowerManagement Capability ID (POWERCAPID)
PME CTRL STATUS (PMECTRLSTATUS)
PCIDEVIDLE CAP RECORD (PCIDEVIDLE_CAP_RECORD)
DEVID VEND SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)
D0I3 CONTROL SW LTR MMIO REG (D0I3_CONTROL_SW_LTR_MMIO_REG)
DEVICE IDLE POINTER REG (DEVICE_IDLE_POINTER_REG)
D0I3 MAX POW LAT PG CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG)
GEN REG RW1 (GEN_REGRW1)
GEN REG RW2 (GEN_REGRW2)
GEN REG RW3 (GEN_REGRW3)
GEN REG RW4 (GEN_REGRW4)
GEN INPUT REG (GEN_INPUT_REG)
RTC Index
RTC Index Seconds Value (Sec) Seconds Alarm (Sec_Alarm) Minutes Value (Minutes) Minutes Alarm (Minutes_Alarm) Hours Value (Hours) Hours Alarm (Hours_Alarm) Day Of Week (Day_of_Week) Day Of Month (Day_of_Month) Month Value (Month) Year Value (Year) Register A (Register_A) Register B General Configuration (Register_B) Register C Flag Register (Register_C) Register D Flag Register (Register_D) 114 Bytes Of Lower User RAM (Register_E) 128 Bytes Of Upper User RAM (Register_80)
Seconds Value (Sec)
Seconds Alarm (Sec_Alarm)
Minutes Value (Minutes)
Minutes Alarm (Minutes_Alarm)
Hours Value (Hours)
Hours Alarm (Hours_Alarm)
Day Of Week (Day_of_Week)
Day Of Month (Day_of_Month)
Month Value (Month)
Year Value (Year)
Register A (Register_A)
Register B General Configuration (Register_B)
Register C Flag Register (Register_C)
Register D Flag Register (Register_D)
114 Bytes Of Lower User RAM (Register_E)
128 Bytes Of Upper User RAM (Register_80)
RTC PCR
RTC PCR RTC Configuration (RC) Backed Up Control (BUC) SAI Policy Group 1 Control Policy (SAIPG1_CP_LO) RTC Update In Progress SMI Control (UIPSMI)
RTC Configuration (RC)
Backed Up Control (BUC)
SAI Policy Group 1 Control Policy (SAIPG1_CP_LO)
RTC Update In Progress SMI Control (UIPSMI)
SATA ABAR
SATA ABAR HBA Capabilities (GHC_CAP) Global HBA Control (GHC) Interrupt Status Register (IS) Ports Implemented (GHC_PI) AHCI Version (VS) Enclosure Management Location (EM_LOC) Enclosure Management Control (EM_CTL) HBA Capabilities Extended (GHC_CAP2) Vendor Specific (VSP) Vendor-Specific Capabilities Register (VS_CAP) RAID Platform ID (RPID) Premium Feature Block (PFB) SW Feature Mask (SFM)
HBA Capabilities (GHC_CAP)
Global HBA Control (GHC)
Interrupt Status Register (IS)
Ports Implemented (GHC_PI)
AHCI Version (VS)
Enclosure Management Location (EM_LOC)
Enclosure Management Control (EM_CTL)
HBA Capabilities Extended (GHC_CAP2)
Vendor Specific (VSP)
Vendor-Specific Capabilities Register (VS_CAP)
RAID Platform ID (RPID)
Premium Feature Block (PFB)
SW Feature Mask (SFM)
SATA AIDPBA
SATA AIDPBA AHCI Index Register (INDEX) AHCI Data Register (DATA)
AHCI Index Register (INDEX)
AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA Initialization (SIR) Index Squelch Circuit Disable (PTM1) SATA Dynamic Clock Gating Enable (PTM4) SATA MPHY Dynamic Power Gating Enable (PTM5)
Squelch Circuit Disable (PTM1)
SATA Dynamic Clock Gating Enable (PTM4)
SATA MPHY Dynamic Power Gating Enable (PTM5)
SATA MXPBA
SATA MXPBA MSI-X Pending Bit Array QW 0 (MXPQW0_DW0) MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA MXTBA MSI-X Table Entries 0 Message Lower Address (MXTE0MLA) MSI-X Table Entries 0 Message Upper Address (MXTE0MUA) MSI-X Table Entries 0 Message Data (MXTE0MD) MSI-X Table Entries 0 Vector Control (MXTE0VC) MSI-X Table Entries 1 Message Lower Address (MXTE1MLA) MSI-X Table Entries 1 Message Upper Address (MXTE1MUA) MSI-X Table Entries 1 Message Data (MXTE1MD) MSI-X Table Entries 1 Vector Control (MXTE1VC) MSI-X Table Entries 2 Message Lower Address (MXTE2MLA) MSI-X Table Entries 2 Message Upper Address (MXTE2MUA) MSI-X Table Entries 2 Message Data (MXTE2MD) MSI-X Table Entries 2 Vector Control (MXTE2VC) MSI-X Table Entries 3 Message Lower Address (MXTE3MLA) MSI-X Table Entries 3 Message Upper Address (MXTE3MUA) MSI-X Table Entries 3 Message Data (MXTE3MD) MSI-X Table Entries 3 Vector Control (MXTE3VC) MSI-X Table Entries 4 Message Lower Address (MXTE4MLA) MSI-X Table Entries 4 Message Upper Address (MXTE4MUA) MSI-X Table Entries 4 Message Data (MXTE4MD) MSI-X Table Entries 4 Vector Control (MXTE4VC) MSI-X Table Entries 5 Message Lower Address (MXTE5MLA) MSI-X Table Entries 5 Message Upper Address (MXTE5MUA) MSI-X Table Entries 5 Message Data (MXTE5MD) MSI-X Table Entries 5 Vector Control (MXTE5VC) MSI-X Table Entries 6 Message Lower Address (MXTE6MLA) MSI-X Table Entries 6 Message Upper Address (MXTE6MUA) MSI-X Table Entries 6 Message Data (MXTE6MD) MSI-X Table Entries 6 Vector Control (MXTE6VC) MSI-X Table Entries 7 Message Lower Address (MXTE7MLA) MSI-X Table Entries 7 Message Upper Address (MXTE7MUA) MSI-X Table Entries 7 Message Data (MXTE7MD) MSI-X Table Entries 7 Vector Control (MXTE7VC)
MSI-X Table Entries 0 Message Lower Address (MXTE0MLA)
MSI-X Table Entries 0 Message Upper Address (MXTE0MUA)
MSI-X Table Entries 0 Message Data (MXTE0MD)
MSI-X Table Entries 0 Vector Control (MXTE0VC)
MSI-X Table Entries 1 Message Lower Address (MXTE1MLA)
MSI-X Table Entries 1 Message Upper Address (MXTE1MUA)
MSI-X Table Entries 1 Message Data (MXTE1MD)
MSI-X Table Entries 1 Vector Control (MXTE1VC)
MSI-X Table Entries 2 Message Lower Address (MXTE2MLA)
MSI-X Table Entries 2 Message Upper Address (MXTE2MUA)
MSI-X Table Entries 2 Message Data (MXTE2MD)
MSI-X Table Entries 2 Vector Control (MXTE2VC)
MSI-X Table Entries 3 Message Lower Address (MXTE3MLA)
MSI-X Table Entries 3 Message Upper Address (MXTE3MUA)
MSI-X Table Entries 3 Message Data (MXTE3MD)
MSI-X Table Entries 3 Vector Control (MXTE3VC)
MSI-X Table Entries 4 Message Lower Address (MXTE4MLA)
MSI-X Table Entries 4 Message Upper Address (MXTE4MUA)
MSI-X Table Entries 4 Message Data (MXTE4MD)
MSI-X Table Entries 4 Vector Control (MXTE4VC)
MSI-X Table Entries 5 Message Lower Address (MXTE5MLA)
MSI-X Table Entries 5 Message Upper Address (MXTE5MUA)
MSI-X Table Entries 5 Message Data (MXTE5MD)
MSI-X Table Entries 5 Vector Control (MXTE5VC)
MSI-X Table Entries 6 Message Lower Address (MXTE6MLA)
MSI-X Table Entries 6 Message Upper Address (MXTE6MUA)
MSI-X Table Entries 6 Message Data (MXTE6MD)
MSI-X Table Entries 6 Vector Control (MXTE6VC)
MSI-X Table Entries 7 Message Lower Address (MXTE7MLA)
MSI-X Table Entries 7 Message Upper Address (MXTE7MUA)
MSI-X Table Entries 7 Message Data (MXTE7MD)
MSI-X Table Entries 7 Vector Control (MXTE7VC)
SATA PCI Configuration
SATA PCI Configuration Identifiers (ID) Command (CMD) Device Status (STS) Revision ID (RID) Programming Interface (PI) Class Code (CC) Cache Line Size (CLS) Master Latency Timer (MLT) Header Type (HTYPE) MSI-X Table Base Address (MXTBA) MSI-X Pending Bit Array Base Address (MXPBA) Secondary Command Block Base Address (SCMDBA) Secondary Control Block Base Address (SCTLBA) AHCI Index Data Pair Base Address (AIDPBA) AHCI Base Address (ABAR) Sub System Identifiers (SS) Capabilities Pointer (CAP) Interrupt Information (INTR) PCI Power Management Capability ID (PID) PCI Power Management Capabilities (PC) PCI Power Management Control And Status (PMCS) Message Signalled Interrupt Identifier (MID) Message Signalled Interrupt Message Control (MC) Message Signalled Interrupt Message Address (MA) Message Signalled Interrupt Message Data (MD) Port Mapping Register (MAP) Port Control And Status (PCS) SATA General Configuration (SATAGC) SATA Initialization Register Index (SIRI) SATA Initialization Register Data (SIRD) Serial ATA Capability Register 0 (SATACR0) Serial ATA Capability Register 1 (SATACR1) Scratch Pad (SP) MSI-X Identifiers (MXID) MSI-X Message Control (MXC) MSI-X Table Offset And Table BIR (MXT) MSI-X PBA Offset And PBA BIR (MXP) BIST FIS Control/Status (BFCS) BIST FIS Transmit Data 1 (BFTD1) BIST FIS Transmit Data 2 (BFTD2)
Identifiers (ID)
Command (CMD)
Device Status (STS)
Revision ID (RID)
Programming Interface (PI)
Class Code (CC)
Cache Line Size (CLS)
Master Latency Timer (MLT)
Header Type (HTYPE)
MSI-X Table Base Address (MXTBA)
MSI-X Pending Bit Array Base Address (MXPBA)
Secondary Command Block Base Address (SCMDBA)
Secondary Control Block Base Address (SCTLBA)
AHCI Index Data Pair Base Address (AIDPBA)
AHCI Base Address (ABAR)
Sub System Identifiers (SS)
Capabilities Pointer (CAP)
Interrupt Information (INTR)
PCI Power Management Capability ID (PID)
PCI Power Management Capabilities (PC)
PCI Power Management Control And Status (PMCS)
Message Signalled Interrupt Identifier (MID)
Message Signalled Interrupt Message Control (MC)
Message Signalled Interrupt Message Address (MA)
Message Signalled Interrupt Message Data (MD)
Port Mapping Register (MAP)
Port Control And Status (PCS)
SATA General Configuration (SATAGC)
SATA Initialization Register Index (SIRI)
SATA Initialization Register Data (SIRD)
Serial ATA Capability Register 0 (SATACR0)
Serial ATA Capability Register 1 (SATACR1)
Scratch Pad (SP)
MSI-X Identifiers (MXID)
MSI-X Message Control (MXC)
MSI-X Table Offset And Table BIR (MXT)
MSI-X PBA Offset And PBA BIR (MXP)
BIST FIS Control/Status (BFCS)
BIST FIS Transmit Data 1 (BFTD1)
BIST FIS Transmit Data 2 (BFTD2)
SATA Port 0 ABAR
SATA Port 0 ABAR Port 0 Command List Base Address (PxCLB0) Port 0 Command List Base Address Upper 32-bits (PxCLBU0) Port 0 FIS Base Address (PxFB0) Port 0 FIS Base Address Upper 32-bits (PxFBU0) Port 0 Interrupt Status (PxIS0) Port 0 Interrupt Enable (PxIE0) Port 0 Command (PxCMD0) Port 0 Task File Data (PxTFD0) Port 0 Signature (PxSIG0) Port 0 Serial ATA Status (PxSSTS0) Port 0 Serial ATA Control (PxSCTL0) Port 0 Serial ATA Error (PxSERR0) Port 0 Serial ATA Active (PxSACT0) Port 0 Commands Issued (PxCI0) Port 0 SNotification (PxSNTF0) Port 0 Device Sleep (PxDEVSLP0)
Port 0 Command List Base Address (PxCLB0)
Port 0 Command List Base Address Upper 32-bits (PxCLBU0)
Port 0 FIS Base Address (PxFB0)
Port 0 FIS Base Address Upper 32-bits (PxFBU0)
Port 0 Interrupt Status (PxIS0)
Port 0 Interrupt Enable (PxIE0)
Port 0 Command (PxCMD0)
Port 0 Task File Data (PxTFD0)
Port 0 Signature (PxSIG0)
Port 0 Serial ATA Status (PxSSTS0)
Port 0 Serial ATA Control (PxSCTL0)
Port 0 Serial ATA Error (PxSERR0)
Port 0 Serial ATA Active (PxSACT0)
Port 0 Commands Issued (PxCI0)
Port 0 SNotification (PxSNTF0)
Port 0 Device Sleep (PxDEVSLP0)
SATA Port 1 ABAR
SATA Port 1 ABAR Port 1 Command List Base Address (PxCLB1) Port 1 Command List Base Address Upper 32-bits (PxCLBU1) Port 1 FIS Base Address (PxFB1) Port 1 FIS Base Address Upper 32-bits (PxFBU1) Port 1 Interrupt Status (PxIS1) Port 1 Interrupt Enable (PxIE1) Port 1 Command (PxCMD1) Port 1 Task File Data (PxTFD1) Port 1 Signature (PxSIG1) Port 1 Serial ATA Status (PxSSTS1) Port 1 Serial ATA Control (PxSCTL1) Port 1 Serial ATA Error (PxSERR1) Port 1 Serial ATA Active (PxSACT1) Port 1 Commands Issued (PxCI1) Port 1 SNotification (PxSNTF1) Port 1 Device Sleep (PxDEVSLP1)
Port 1 Command List Base Address (PxCLB1)
Port 1 Command List Base Address Upper 32-bits (PxCLBU1)
Port 1 FIS Base Address (PxFB1)
Port 1 FIS Base Address Upper 32-bits (PxFBU1)
Port 1 Interrupt Status (PxIS1)
Port 1 Interrupt Enable (PxIE1)
Port 1 Command (PxCMD1)
Port 1 Task File Data (PxTFD1)
Port 1 Signature (PxSIG1)
Port 1 Serial ATA Status (PxSSTS1)
Port 1 Serial ATA Control (PxSCTL1)
Port 1 Serial ATA Error (PxSERR1)
Port 1 Serial ATA Active (PxSACT1)
Port 1 Commands Issued (PxCI1)
Port 1 SNotification (PxSNTF1)
Port 1 Device Sleep (PxDEVSLP1)
SATA Port 2 ABAR
SATA Port 2 ABAR Port 2 Command List Base Address (PxCLB2) Port 2 Command List Base Address Upper 32-bits (PxCLBU2) Port 2 FIS Base Address (PxFB2) Port 2 FIS Base Address Upper 32-bits (PxFBU2) Port 2 Interrupt Status (PxIS2) Port 2 Interrupt Enable (PxIE2) Port 2 Command (PxCMD2) Port 2 Task File Data (PxTFD2) Port 2 Signature (PxSIG2) Port 2 Serial ATA Status (PxSSTS2) Port 2 Serial ATA Control (PxSCTL2) Port 2 Serial ATA Error (PxSERR2) Port 2 Serial ATA Active (PxSACT2) Port 2 Commands Issued (PxCI2) Port 2 SNotification (PxSNTF2) Port 2 Device Sleep (PxDEVSLP2)
Port 2 Command List Base Address (PxCLB2)
Port 2 Command List Base Address Upper 32-bits (PxCLBU2)
Port 2 FIS Base Address (PxFB2)
Port 2 FIS Base Address Upper 32-bits (PxFBU2)
Port 2 Interrupt Status (PxIS2)
Port 2 Interrupt Enable (PxIE2)
Port 2 Command (PxCMD2)
Port 2 Task File Data (PxTFD2)
Port 2 Signature (PxSIG2)
Port 2 Serial ATA Status (PxSSTS2)
Port 2 Serial ATA Control (PxSCTL2)
Port 2 Serial ATA Error (PxSERR2)
Port 2 Serial ATA Active (PxSACT2)
Port 2 Commands Issued (PxCI2)
Port 2 SNotification (PxSNTF2)
Port 2 Device Sleep (PxDEVSLP2)
SATA Port 3 ABAR
SATA Port 3 ABAR Port 3 Command List Base Address (PxCLB3) Port 3 Command List Base Address Upper 32-bits (PxCLBU3) Port 3 FIS Base Address (PxFB3) Port 3 FIS Base Address Upper 32-bits (PxFBU3) Port 3 Interrupt Status (PxIS3) Port 3 Interrupt Enable (PxIE3) Port 3 Command (PxCMD3) Port 3 Task File Data (PxTFD3) Port 3 Signature (PxSIG3) Port 3 Serial ATA Status (PxSSTS3) Port 3 Serial ATA Control (PxSCTL3) Port 3 Serial ATA Error (PxSERR3) Port 3 Serial ATA Active (PxSACT3) Port 3 Commands Issued (PxCI3) Port 3 SNotification (PxSNTF3) Port 3 Device Sleep (PxDEVSLP3)
Port 3 Command List Base Address (PxCLB3)
Port 3 Command List Base Address Upper 32-bits (PxCLBU3)
Port 3 FIS Base Address (PxFB3)
Port 3 FIS Base Address Upper 32-bits (PxFBU3)
Port 3 Interrupt Status (PxIS3)
Port 3 Interrupt Enable (PxIE3)
Port 3 Command (PxCMD3)
Port 3 Task File Data (PxTFD3)
Port 3 Signature (PxSIG3)
Port 3 Serial ATA Status (PxSSTS3)
Port 3 Serial ATA Control (PxSCTL3)
Port 3 Serial ATA Error (PxSERR3)
Port 3 Serial ATA Active (PxSACT3)
Port 3 Commands Issued (PxCI3)
Port 3 SNotification (PxSNTF3)
Port 3 Device Sleep (PxDEVSLP3)
SATA Port 4 ABAR
SATA Port 4 ABAR Port 4 Command List Base Address (PxCLB4) Port 4 Command List Base Address Upper 32-bits (PxCLBU4) Port 4 FIS Base Address (PxFB4) Port 4 FIS Base Address Upper 32-bits (PxFBU4) Port 4 Interrupt Status (PxIS4) Port 4 Interrupt Enable (PxIE4) Port 4 Command (PxCMD4) Port 4 Task File Data (PxTFD4) Port 4 Signature (PxSIG4) Port 4 Serial ATA Status (PxSSTS4) Port 4 Serial ATA Control (PxSCTL4) Port 4 Serial ATA Error (PxSERR4) Port 4 Serial ATA Active (PxSACT4) Port 4 Commands Issued (PxCI4) Port 4 SNotification (PxSNTF4) Port 4 Device Sleep (PxDEVSLP4)
Port 4 Command List Base Address (PxCLB4)
Port 4 Command List Base Address Upper 32-bits (PxCLBU4)
Port 4 FIS Base Address (PxFB4)
Port 4 FIS Base Address Upper 32-bits (PxFBU4)
Port 4 Interrupt Status (PxIS4)
Port 4 Interrupt Enable (PxIE4)
Port 4 Command (PxCMD4)
Port 4 Task File Data (PxTFD4)
Port 4 Signature (PxSIG4)
Port 4 Serial ATA Status (PxSSTS4)
Port 4 Serial ATA Control (PxSCTL4)
Port 4 Serial ATA Error (PxSERR4)
Port 4 Serial ATA Active (PxSACT4)
Port 4 Commands Issued (PxCI4)
Port 4 SNotification (PxSNTF4)
Port 4 Device Sleep (PxDEVSLP4)
SATA Port 5 ABAR
SATA Port 5 ABAR Port 5 Command List Base Address (PxCLB5) Port 5 Command List Base Address Upper 32-bits (PxCLBU5) Port 5 FIS Base Address (PxFB5) Port 5 FIS Base Address Upper 32-bits (PxFBU5) Port 5 Interrupt Status (PxIS5) Port 5 Interrupt Enable (PxIE5) Port 5 Command (PxCMD5) Port 5 Task File Data (PxTFD5) Port 5 Signature (PxSIG5) Port 5 Serial ATA Status (PxSSTS5) Port 5 Serial ATA Control (PxSCTL5) Port 5 Serial ATA Error (PxSERR5) Port 5 Serial ATA Active (PxSACT5) Port 5 Commands Issued (PxCI5) Port 5 SNotification (PxSNTF5) Port 5 Device Sleep (PxDEVSLP5)
Port 5 Command List Base Address (PxCLB5)
Port 5 Command List Base Address Upper 32-bits (PxCLBU5)
Port 5 FIS Base Address (PxFB5)
Port 5 FIS Base Address Upper 32-bits (PxFBU5)
Port 5 Interrupt Status (PxIS5)
Port 5 Interrupt Enable (PxIE5)
Port 5 Command (PxCMD5)
Port 5 Task File Data (PxTFD5)
Port 5 Signature (PxSIG5)
Port 5 Serial ATA Status (PxSSTS5)
Port 5 Serial ATA Control (PxSCTL5)
Port 5 Serial ATA Error (PxSERR5)
Port 5 Serial ATA Active (PxSACT5)
Port 5 Commands Issued (PxCI5)
Port 5 SNotification (PxSNTF5)
Port 5 Device Sleep (PxDEVSLP5)
SATA Port 6 ABAR
SATA Port 6 ABAR Port 6 Command List Base Address (PxCLB6) Port 6 Command List Base Address Upper 32-bits (PxCLBU6) Port 6 FIS Base Address (PxFB6) Port 6 FIS Base Address Upper 32-bits (PxFBU6) Port 6 Interrupt Status (PxIS6) Port 6 Interrupt Enable (PxIE6) Port 6 Command (PxCMD6) Port 6 Task File Data (PxTFD6) Port 6 Signature (PxSIG6) Port 6 Serial ATA Status (PxSSTS6) Port 6 Serial ATA Control (PxSCTL6) Port 6 Serial ATA Error (PxSERR6) Port 6 Serial ATA Active (PxSACT6) Port 6 Commands Issued (PxCI6) Port 6 SNotification (PxSNTF6) Port 6 Device Sleep (PxDEVSLP6)
Port 6 Command List Base Address (PxCLB6)
Port 6 Command List Base Address Upper 32-bits (PxCLBU6)
Port 6 FIS Base Address (PxFB6)
Port 6 FIS Base Address Upper 32-bits (PxFBU6)
Port 6 Interrupt Status (PxIS6)
Port 6 Interrupt Enable (PxIE6)
Port 6 Command (PxCMD6)
Port 6 Task File Data (PxTFD6)
Port 6 Signature (PxSIG6)
Port 6 Serial ATA Status (PxSSTS6)
Port 6 Serial ATA Control (PxSCTL6)
Port 6 Serial ATA Error (PxSERR6)
Port 6 Serial ATA Active (PxSACT6)
Port 6 Commands Issued (PxCI6)
Port 6 SNotification (PxSNTF6)
Port 6 Device Sleep (PxDEVSLP6)
SATA Port 7 ABAR
SATA Port 7 ABAR Port 7 Command List Base Address (PxCLB7) Port 7 Command List Base Address Upper 32-bits (PxCLBU7) Port 7 FIS Base Address (PxFB7) Port 7 FIS Base Address Upper 32-bits (PxFBU7) Port 7 Interrupt Status (PxIS7) Port 7 Interrupt Enable (PxIE7) Port 7 Command (PxCMD7) Port 7 Task File Data (PxTFD7) Port 7 Signature (PxSIG7) Port 7 Serial ATA Status (PxSSTS7) Port 7 Serial ATA Control (PxSCTL7) Port 7 Serial ATA Error (PxSERR7) Port 7 Serial ATA Active (PxSACT7) Port 7 Commands Issued (PxCI7) Port 7 SNotification (PxSNTF7) Port 7 Device Sleep (PxDEVSLP7)
Port 7 Command List Base Address (PxCLB7)
Port 7 Command List Base Address Upper 32-bits (PxCLBU7)
Port 7 FIS Base Address (PxFB7)
Port 7 FIS Base Address Upper 32-bits (PxFBU7)
Port 7 Interrupt Status (PxIS7)
Port 7 Interrupt Enable (PxIE7)
Port 7 Command (PxCMD7)
Port 7 Task File Data (PxTFD7)
Port 7 Signature (PxSIG7)
Port 7 Serial ATA Status (PxSSTS7)
Port 7 Serial ATA Control (PxSCTL7)
Port 7 Serial ATA Error (PxSERR7)
Port 7 Serial ATA Active (PxSACT7)
Port 7 Commands Issued (PxCI7)
Port 7 SNotification (PxSNTF7)
Port 7 Device Sleep (PxDEVSLP7)
SMBus MMIO and I/O
SMBus MMIO and I/O Host Status Register Address (HSTS) Host Control Register (HCTL) Host Command Register (HCMD) Transmit Target Address Register (TSA) Data 0 Register (HD0) Data 1 Register (HD1) Host Block Data (HBD) Packet Error Check Data Register (PEC) Receive Target Address Register (RSA) Target Data Register (SD) Auxiliary Status (AUXS) Auxiliary Control (AUXC) SMLINK_PIN_CTL Register (SMLC) SMBUS_PIN_CTL Register (SMBC) Target Status Register (SSTS) Target Command Register (SCMD) Notify Device Address Register (NDA) Notify Data Low Byte Register (NDLB) Notify Data High Byte Register (NDHB)
Host Status Register Address (HSTS)
Host Control Register (HCTL)
Host Command Register (HCMD)
Transmit Target Address Register (TSA)
Data 0 Register (HD0)
Data 1 Register (HD1)
Host Block Data (HBD)
Packet Error Check Data Register (PEC)
Receive Target Address Register (RSA)
Target Data Register (SD)
Auxiliary Status (AUXS)
Auxiliary Control (AUXC)
SMLINK_PIN_CTL Register (SMLC)
SMBUS_PIN_CTL Register (SMBC)
Target Status Register (SSTS)
Target Command Register (SCMD)
Notify Device Address Register (NDA)
Notify Data Low Byte Register (NDLB)
Notify Data High Byte Register (NDHB)
SMBus PCI Configuration
SMBus PCI Configuration Vendor ID (VID) Device ID (DID) Command Register (CMD) Device Status (DS) Revision ID (RID) Programming Interface (PI) Sub Class Code (SCC) Base Class Code (BCC) SMBus Memory Base Address_31_0 (SMBMBAR_31_0) SMBus Memory Base Address_63_32 (SMBMBAR_63_32) SMB Base Address (SBA) Subsystem Vendor Identifiers (SVID) Subsystem Identifiers (SID) Interrupt Line (INTLN) Interrupt Pin (INTPN) Host Configuration (HCFG) TCO Base Address (TCOBASE) TCO Control (TCOCTL) Unsupported Request Error Status (URES) Unsupported Request Error Control (UREC)
Vendor ID (VID)
Device ID (DID)
Command Register (CMD)
Device Status (DS)
Revision ID (RID)
Programming Interface (PI)
Sub Class Code (SCC)
Base Class Code (BCC)
SMBus Memory Base Address_31_0 (SMBMBAR_31_0)
SMBus Memory Base Address_63_32 (SMBMBAR_63_32)
SMB Base Address (SBA)
Subsystem Vendor Identifiers (SVID)
Subsystem Identifiers (SID)
Interrupt Line (INTLN)
Interrupt Pin (INTPN)
Host Configuration (HCFG)
TCO Base Address (TCOBASE)
TCO Control (TCOCTL)
Unsupported Request Error Status (URES)
Unsupported Request Error Control (UREC)
SMBus PCR
SMBus PCR TCO Configuration (TCOCFG) General Control (GC) Power Control Enable (PCE)
TCO Configuration (TCOCFG)
General Control (GC)
Power Control Enable (PCE)
SMBus TCO I/O
SMBus TCO I/O TCO_RLD Register (TRLD) TCO_DAT_IN Register (TDI) TCO_DAT_OUT Register (TDO) TCO1_STS Register (TSTS1) TCO2_STS Register (TSTS2) TCO1_CNT Register (TCTL1) TCO2_CNT Register (TCTL2) TCO Message Registers (TMSG) TCO_WDSTATUS Register (TWDS) LEGACY_ELIM Register (LE) TCO_TMR Register (TTMR)
TCO_RLD Register (TRLD)
TCO_DAT_IN Register (TDI)
TCO_DAT_OUT Register (TDO)
TCO1_STS Register (TSTS1)
TCO2_STS Register (TSTS2)
TCO1_CNT Register (TCTL1)
TCO2_CNT Register (TCTL2)
TCO Message Registers (TMSG)
TCO_WDSTATUS Register (TWDS)
LEGACY_ELIM Register (LE)
TCO_TMR Register (TTMR)
SPI MMIO
SPI MMIO BIOS Flash Primary Region (BIOS_BFPREG) Hardware Sequencing Flash Status and Control (BIOS_HSFSTS_CTL) Flash Address (BIOS_FADDR) Discrete Lock Bits (BIOS_DLOCK) Flash Data (BIOS_FDATA0) Flash Data (BIOS_FDATA1) Flash Data (BIOS_FDATA2) Flash Data (BIOS_FDATA3) Flash Data (BIOS_FDATA4) Flash Data (BIOS_FDATA5) Flash Data (BIOS_FDATA6) Flash Data (BIOS_FDATA7) Flash Data (BIOS_FDATA8) Flash Data (BIOS_FDATA9) Flash Data (BIOS_FDATA10) Flash Data (BIOS_FDATA11) Flash Data (BIOS_FDATA12) Flash Data (BIOS_FDATA13) Flash Data (BIOS_FDATA14) Flash Data (BIOS_FDATA15) Flash Region Access Permissions (BIOS_FRACC) Flash Region (BIOS_FREG0) Flash Region (BIOS_FREG1) Flash Region (BIOS_FREG2) Flash Region (BIOS_FREG3) Flash Region (BIOS_FREG4) Flash Region (BIOS_FREG5) Flash Region (BIOS_FREG6) Flash Region (BIOS_FREG7) Flash Region (BIOS_FREG8) Flash Region (BIOS_FREG9) Flash Region (BIOS_FREG10) Flash Region (BIOS_FREG11) Flash Protected Range (BIOS_FPR0) Flash Protected Range (BIOS_FPR1) Flash Protected Range (BIOS_FPR2) Flash Protected Range (BIOS_FPR3) Flash Protected Range (BIOS_FPR4) Global Protected Range 0 (BIOS_GPR0) Secondary Flash Region Access Permissions (BIOS_SFRACC) Flash Descriptor Observability Control (BIOS_FDOC) Flash Descriptor Observability Data (BIOS_FDOD) Additional Flash Control (BIOS_AFC) Vendor Specific Component Capabilities for Component 0 (BIOS_SFDP0_VSCC0) Vendor Specific Component Capabilities for Component 1 (BIOS_SFDP1_VSCC1) Parameter Table Index (BIOS_PTINX) Parameter Table Data (BIOS_PTDATA) SPI Bus Requester Status (BIOS_SBRS) Flash Region (BIOS_FREG12) Flash Region (BIOS_FREG13) Flash Region (BIOS_FREG14) Flash Region (BIOS_FREG15)
BIOS Flash Primary Region (BIOS_BFPREG)
Hardware Sequencing Flash Status and Control (BIOS_HSFSTS_CTL)
Flash Address (BIOS_FADDR)
Discrete Lock Bits (BIOS_DLOCK)
Flash Data (BIOS_FDATA0)
Flash Data (BIOS_FDATA1)
Flash Data (BIOS_FDATA2)
Flash Data (BIOS_FDATA3)
Flash Data (BIOS_FDATA4)
Flash Data (BIOS_FDATA5)
Flash Data (BIOS_FDATA6)
Flash Data (BIOS_FDATA7)
Flash Data (BIOS_FDATA8)
Flash Data (BIOS_FDATA9)
Flash Data (BIOS_FDATA10)
Flash Data (BIOS_FDATA11)
Flash Data (BIOS_FDATA12)
Flash Data (BIOS_FDATA13)
Flash Data (BIOS_FDATA14)
Flash Data (BIOS_FDATA15)
Flash Region Access Permissions (BIOS_FRACC)
Flash Region (BIOS_FREG0)
Flash Region (BIOS_FREG1)
Flash Region (BIOS_FREG2)
Flash Region (BIOS_FREG3)
Flash Region (BIOS_FREG4)
Flash Region (BIOS_FREG5)
Flash Region (BIOS_FREG6)
Flash Region (BIOS_FREG7)
Flash Region (BIOS_FREG8)
Flash Region (BIOS_FREG9)
Flash Region (BIOS_FREG10)
Flash Region (BIOS_FREG11)
Flash Protected Range (BIOS_FPR0)
Flash Protected Range (BIOS_FPR1)
Flash Protected Range (BIOS_FPR2)
Flash Protected Range (BIOS_FPR3)
Flash Protected Range (BIOS_FPR4)
Global Protected Range 0 (BIOS_GPR0)
Secondary Flash Region Access Permissions (BIOS_SFRACC)
Flash Descriptor Observability Control (BIOS_FDOC)
Flash Descriptor Observability Data (BIOS_FDOD)
Additional Flash Control (BIOS_AFC)
Vendor Specific Component Capabilities for Component 0 (BIOS_SFDP0_VSCC0)
Vendor Specific Component Capabilities for Component 1 (BIOS_SFDP1_VSCC1)
Parameter Table Index (BIOS_PTINX)
Parameter Table Data (BIOS_PTDATA)
SPI Bus Requester Status (BIOS_SBRS)
Flash Region (BIOS_FREG12)
Flash Region (BIOS_FREG13)
Flash Region (BIOS_FREG14)
Flash Region (BIOS_FREG15)
SPI PCI Configuration
SPI PCI Configuration Device ID and Vendor ID (BIOS_SPI_DID_VID) Status and Command (BIOS_SPI_STS_CMD) Revision ID and Class Code (BIOS_SPI_CC_RID) BIST, Header Type, Latency Timer, Cache Line Size (BIOS_SPI_BIST_HTYPE_LT_CLS) SPI BAR0 MMIO (BIOS_SPI_BAR0) Subsystem and Vendor ID (BIOS_SPI_SID_SVID) BIOS Direct Read DMA Base Address High (BIOS_RD_DMA_BA_HI) BIOS Direct Read DMA Base Address (BIOS_RD_DMA_BA) BIOS Direct Read DMA Base Offset (BIOS_RD_DMA_BASE_OFFSET) BIOS Direct Read DMA Control (BIOS_RD_DMA_STS) SPI Unsupported Request Status (BIOS_SPI_UR_STS_CTL) BIOS Decode Enable (BIOS_SPI_BDE) BIOS Control (BIOS_SPI_BC) SPI BAR1 MMIO (BIOS_SPI_BAR1)
Device ID and Vendor ID (BIOS_SPI_DID_VID)
Status and Command (BIOS_SPI_STS_CMD)
Revision ID and Class Code (BIOS_SPI_CC_RID)
BIST, Header Type, Latency Timer, Cache Line Size (BIOS_SPI_BIST_HTYPE_LT_CLS)
SPI BAR0 MMIO (BIOS_SPI_BAR0)
Subsystem and Vendor ID (BIOS_SPI_SID_SVID)
BIOS Direct Read DMA Base Address High (BIOS_RD_DMA_BA_HI)
BIOS Direct Read DMA Base Address (BIOS_RD_DMA_BA)
BIOS Direct Read DMA Base Offset (BIOS_RD_DMA_BASE_OFFSET)
BIOS Direct Read DMA Control (BIOS_RD_DMA_STS)
SPI Unsupported Request Status (BIOS_SPI_UR_STS_CTL)
BIOS Decode Enable (BIOS_SPI_BDE)
BIOS Control (BIOS_SPI_BC)
SPI BAR1 MMIO (BIOS_SPI_BAR1)
THC MMIO Common
THC MMIO Common Device Idle Control Register (THC_M_CMN_DEVIDLECTRL) THC LTR Control Register (THC_M_CMN_LTR_CTRL)
Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC MMIO Port Touch Host Controller Control Register (THC_M_PRT_CONTROL) THC SPI Bus Configuration Register (THC_M_PRT_SPI_CFG) THC SPI Bus Read Opcode Register (THC_M_PRT_SPI_ICRRD_OPCODE) THC SPI Bus Read Opcode Register (THC_M_PRT_SPI_DMARD_OPCODE) THC SPI Bus Write Opcode Register (THC_M_PRT_SPI_WR_OPCODE) THC Interrupt Enable Register (THC_M_PRT_INT_EN) THC Interrupt Status Register (THC_M_PRT_INT_STATUS) THC Error Cause Register (THC_M_PRT_ERR_CAUSE) THC SW sequencing Control (THC_M_PRT_SW_SEQ_CNTRL) THC SW sequencing Status (THC_M_PRT_SW_SEQ_STS) THC SW Sequencing Data DW0 or SPI Address Register (THC_M_PRT_SW_SEQ_DATA0_ADDR) THC SW sequencing Data DW1 (THC_M_PRT_SW_SEQ_DATA1) THC SW sequencing Data DW2 (THC_M_PRT_SW_SEQ_DATA2) THC SW sequencing Data DW3 (THC_M_PRT_SW_SEQ_DATA3) THC SW sequencing Data DW4 (THC_M_PRT_SW_SEQ_DATA4) THC SW sequencing Data DW5 (THC_M_PRT_SW_SEQ_DATA5) THC SW sequencing Data DW6 (THC_M_PRT_SW_SEQ_DATA6) THC SW sequencing Data DW7 (THC_M_PRT_SW_SEQ_DATA7) THC SW sequencing Data DW8 (THC_M_PRT_SW_SEQ_DATA8) THC SW sequencing Data DW9 (THC_M_PRT_SW_SEQ_DATA9) THC SW sequencing Data DW10 (THC_M_PRT_SW_SEQ_DATA10) THC SW sequencing Data DW11 (THC_M_PRT_SW_SEQ_DATA11) THC SW sequencing Data DW12 (THC_M_PRT_SW_SEQ_DATA12) THC SW sequencing Data DW13 (THC_M_PRT_SW_SEQ_DATA13) THC SW sequencing Data DW14 (THC_M_PRT_SW_SEQ_DATA14) THC SW sequencing Data DW15 (THC_M_PRT_SW_SEQ_DATA15) THC SW sequencing Data DW16 (THC_M_PRT_SW_SEQ_DATA16) THC Write PRD Base Address Register Low (THC_M_PRT_WPRD_BA_LOW) THC Write PRD Base Address Register High (THC_M_PRT_WPRD_BA_HI) THC Write DMA Control (THC_M_PRT_WRITE_DMA_CNTRL) THC Write Interrupt Status (THC_M_PRT_WRITE_INT_STS) THC device address for the bulk write (THC_M_PRT_WR_BULK_ADDR) THC Device Interrupt Cause Register Address (THC_M_PRT_DEV_INT_CAUSE_ADDR) THC Device Interrupt Cause Register Value (THC_M_PRT_DEV_INT_CAUSE_REG_VAL) THC TXDMA Frame Count (THC_M_PRT_TX_FRM_CNT) THC TXDMA Packet Count (THC_M_PRT_TXDMA_PKT_CNT) THC Device Interrupt Count on this port (THC_M_PRT_DEVINT_CNT) Touch Device Interrupt Cause register Format Configuration Register 1 (THC_M_PRT_DEVINT_CFG_1) Touch Device Interrupt Cause register Format Configuration Register 2 (THC_M_PRT_DEVINT_CFG_2) THC Read PRD Base Address Low for the 1st RXDMA (THC_M_PRT_RPRD_BA_LOW_1) THC Read PRD Base Address High for the 1st RXDMA (THC_M_PRT_RPRD_BA_HI_1) THC Read PRD Control for the 1st RXDMA (THC_M_PRT_RPRD_CNTRL_1) THC Read DMA Control for the 1st RXDMA (THC_M_PRT_READ_DMA_CNTRL_1) THC Read Interrupt Status for the 1st RXDMA (THC_M_PRT_READ_DMA_INT_STS_1) THC Read DMA Error Register for the 1st RXDMA (THC_M_PRT_READ_DMA_ERR_1) Touch Sequencer GuC Tail Offset Address Low for the 1st RXDMA (THC_M_PRT_GUC_OFFSET_LOW_1) Touch Sequencer GuC Tail Offset Address High for the 1st RXDMA (THC_M_PRT_GUC_OFFSET_HI_1) Touch Host Controller GuC Work Queue Item Size for the 1st RXDMA (THC_M_PRT_GUC_WORKQ_ITEM_SZ_1) Touch Host Controller GuC Control register for the 1st RXDMA (THC_M_PRT_GUC_WORKQ_SZ_1) Touch Sequencer Control for the 1st DMA (THC_M_PRT_TSEQ_CNTRL_1) Touch Sequencer GuC Doorbell Address Low for the 1st RXDMA (THC_M_PRT_GUC_DB_ADDR_LOW_1) Touch Sequencer GuC Doorbell Address High for the 1st RXDMA (THC_M_PRT_GUC_DB_ADDR_HI_1) Touch Sequencer GuC Doorbell Data (THC_M_PRT_GUC_DB_DATA_1) Touch Sequencer GuC Tail Offset Initial Value for the 1st RXDMA (THC_M_PRT_GUC_OFFSET_INITVAL_1) THC Device Address for the bulk/touch data read for the 2nd RXDMA (THC_M_PRT_RD_BULK_ADDR_1) THC Gfx/SW Doorbell Count from the 1st Stream RXDMA on this port (THC_M_PRT_DB_CNT_1) THC Frame Count from the 1st Stream RXDMA on this port (THC_M_PRT_FRM_CNT_1) THC Micro Frame Count from the 1st Stream RXDMA on this port (THC_M_PRT_UFRM_CNT_1) THC Packet Count from the 1st Stream RXDMA on this port (THC_M_PRT_RXDMA_PKT_CNT_1) THC Software Interrupt Count from the 1st Stream RXDMA on this port (THC_M_PRT_SWINT_CNT_1) Touch Sequencer Frame Drop Counter for the 1st RXDMA (THC_M_PRT_FRAME_DROP_CNT_1) THC Coaescing 1 (THC_M_PRT_COALESCE_1) THC Read PRD Base Address Low for the 2nd RXDMA (THC_M_PRT_RPRD_BA_LOW_2) THC Read PRD Base Address High for the 2nd RXDMA (THC_M_PRT_RPRD_BA_HI_2) THC Read PRD Control for the 2nd RXDMA (THC_M_PRT_RPRD_CNTRL_2) THC Read DMA Control for the 2nd RXDMA (THC_M_PRT_READ_DMA_CNTRL_2) THC Read Interrupt Status for the 2nd RXDMA (THC_M_PRT_READ_DMA_INT_STS_2) THC Read DMA Error Register for the 2nd RXDMA (THC_M_PRT_READ_DMA_ERR_2) Touch Sequencer GuC Tail Offset Address Low for the 2nd RXDMA (THC_M_PRT_GUC_OFFSET_LOW_2) Touch Sequencer GuC Tail Offset Address High for the 2nd RXDMA (THC_M_PRT_GUC_OFFSET_HI_2) Touch Host Controller GuC Work Queue Item Size for the 2nd RXDMA (THC_M_PRT_GUC_WORKQ_ITEM_SZ_2) Touch Host Controller GuC Control register for the 2nd RXDMA (THC_M_PRT_GUC_WORKQ_SZ_2) Touch Sequencer Control for the 2nd DMA (THC_M_PRT_TSEQ_CNTRL_2) Touch Sequencer GuC Doorbell Address Low for the 2nd RXDMA (THC_M_PRT_GUC_DB_ADDR_LOW_2) Touch Sequencer GuC Doorbell Address High for the 2nd RXDMA (THC_M_PRT_GUC_DB_ADDR_HI_2) Touch Sequencer GuC Doorbell Data for PRD2 (THC_M_PRT_GUC_DB_DATA_2) Touch Sequencer GuC Tail Offset Initial Value for the 2nd RXDMA (THC_M_PRT_GUC_OFFSET_INITVAL_2) THC Device Address for the bulk/touch data read for the 1st RXDMA (THC_M_PRT_RD_BULK_ADDR_2) THC Gfx/SW Doorbell Count from the 2nd Stream RXDMA on this port (THC_M_PRT_DB_CNT_2) THC Frame Count from the 2nd Stream RXDMA on this port (THC_M_PRT_FRM_CNT_2) THC Micro Frame Count from the 2nd Stream RXDMA on this port (THC_M_PRT_UFRM_CNT_2) THC Packet Count from the 2nd Stream RXDMA on this port (THC_M_PRT_RXDMA_PKT_CNT_2) THC Software Interrupt Count from the 2nd Stream RXDMA on this port (THC_M_PRT_SWINT_CNT_2) Touch Sequencer Frame Drop Counter for the 2nd RXDMA (THC_M_PRT_FRAME_DROP_CNT_2) THC Coaescing 2 (THC_M_PRT_COALESCE_2)
Touch Host Controller Control Register (THC_M_PRT_CONTROL)
THC SPI Bus Configuration Register (THC_M_PRT_SPI_CFG)
THC SPI Bus Read Opcode Register (THC_M_PRT_SPI_ICRRD_OPCODE)
THC SPI Bus Read Opcode Register (THC_M_PRT_SPI_DMARD_OPCODE)
THC SPI Bus Write Opcode Register (THC_M_PRT_SPI_WR_OPCODE)
THC Interrupt Enable Register (THC_M_PRT_INT_EN)
THC Interrupt Status Register (THC_M_PRT_INT_STATUS)
THC Error Cause Register (THC_M_PRT_ERR_CAUSE)
THC SW sequencing Control (THC_M_PRT_SW_SEQ_CNTRL)
THC SW sequencing Status (THC_M_PRT_SW_SEQ_STS)
THC SW Sequencing Data DW0 or SPI Address Register (THC_M_PRT_SW_SEQ_DATA0_ADDR)
THC SW sequencing Data DW1 (THC_M_PRT_SW_SEQ_DATA1)
THC SW sequencing Data DW2 (THC_M_PRT_SW_SEQ_DATA2)
THC SW sequencing Data DW3 (THC_M_PRT_SW_SEQ_DATA3)
THC SW sequencing Data DW4 (THC_M_PRT_SW_SEQ_DATA4)
THC SW sequencing Data DW5 (THC_M_PRT_SW_SEQ_DATA5)
THC SW sequencing Data DW6 (THC_M_PRT_SW_SEQ_DATA6)
THC SW sequencing Data DW7 (THC_M_PRT_SW_SEQ_DATA7)
THC SW sequencing Data DW8 (THC_M_PRT_SW_SEQ_DATA8)
THC SW sequencing Data DW9 (THC_M_PRT_SW_SEQ_DATA9)
THC SW sequencing Data DW10 (THC_M_PRT_SW_SEQ_DATA10)
THC SW sequencing Data DW11 (THC_M_PRT_SW_SEQ_DATA11)
THC SW sequencing Data DW12 (THC_M_PRT_SW_SEQ_DATA12)
THC SW sequencing Data DW13 (THC_M_PRT_SW_SEQ_DATA13)
THC SW sequencing Data DW14 (THC_M_PRT_SW_SEQ_DATA14)
THC SW sequencing Data DW15 (THC_M_PRT_SW_SEQ_DATA15)
THC SW sequencing Data DW16 (THC_M_PRT_SW_SEQ_DATA16)
THC Write PRD Base Address Register Low (THC_M_PRT_WPRD_BA_LOW)
THC Write PRD Base Address Register High (THC_M_PRT_WPRD_BA_HI)
THC Write DMA Control (THC_M_PRT_WRITE_DMA_CNTRL)
THC Write Interrupt Status (THC_M_PRT_WRITE_INT_STS)
THC device address for the bulk write (THC_M_PRT_WR_BULK_ADDR)
THC Device Interrupt Cause Register Address (THC_M_PRT_DEV_INT_CAUSE_ADDR)
THC Device Interrupt Cause Register Value (THC_M_PRT_DEV_INT_CAUSE_REG_VAL)
THC TXDMA Frame Count (THC_M_PRT_TX_FRM_CNT)
THC TXDMA Packet Count (THC_M_PRT_TXDMA_PKT_CNT)
THC Device Interrupt Count on this port (THC_M_PRT_DEVINT_CNT)
Touch Device Interrupt Cause register Format Configuration Register 1 (THC_M_PRT_DEVINT_CFG_1)
Touch Device Interrupt Cause register Format Configuration Register 2 (THC_M_PRT_DEVINT_CFG_2)
THC Read PRD Base Address Low for the 1st RXDMA (THC_M_PRT_RPRD_BA_LOW_1)
THC Read PRD Base Address High for the 1st RXDMA (THC_M_PRT_RPRD_BA_HI_1)
THC Read PRD Control for the 1st RXDMA (THC_M_PRT_RPRD_CNTRL_1)
THC Read DMA Control for the 1st RXDMA (THC_M_PRT_READ_DMA_CNTRL_1)
THC Read Interrupt Status for the 1st RXDMA (THC_M_PRT_READ_DMA_INT_STS_1)
THC Read DMA Error Register for the 1st RXDMA (THC_M_PRT_READ_DMA_ERR_1)
Touch Sequencer GuC Tail Offset Address Low for the 1st RXDMA (THC_M_PRT_GUC_OFFSET_LOW_1)
Touch Sequencer GuC Tail Offset Address High for the 1st RXDMA (THC_M_PRT_GUC_OFFSET_HI_1)
Touch Host Controller GuC Work Queue Item Size for the 1st RXDMA (THC_M_PRT_GUC_WORKQ_ITEM_SZ_1)
Touch Host Controller GuC Control register for the 1st RXDMA (THC_M_PRT_GUC_WORKQ_SZ_1)
Touch Sequencer Control for the 1st DMA (THC_M_PRT_TSEQ_CNTRL_1)
Touch Sequencer GuC Doorbell Address Low for the 1st RXDMA (THC_M_PRT_GUC_DB_ADDR_LOW_1)
Touch Sequencer GuC Doorbell Address High for the 1st RXDMA (THC_M_PRT_GUC_DB_ADDR_HI_1)
Touch Sequencer GuC Doorbell Data (THC_M_PRT_GUC_DB_DATA_1)
Touch Sequencer GuC Tail Offset Initial Value for the 1st RXDMA (THC_M_PRT_GUC_OFFSET_INITVAL_1)
THC Device Address for the bulk/touch data read for the 2nd RXDMA (THC_M_PRT_RD_BULK_ADDR_1)
THC Gfx/SW Doorbell Count from the 1st Stream RXDMA on this port (THC_M_PRT_DB_CNT_1)
THC Frame Count from the 1st Stream RXDMA on this port (THC_M_PRT_FRM_CNT_1)
THC Micro Frame Count from the 1st Stream RXDMA on this port (THC_M_PRT_UFRM_CNT_1)
THC Packet Count from the 1st Stream RXDMA on this port (THC_M_PRT_RXDMA_PKT_CNT_1)
THC Software Interrupt Count from the 1st Stream RXDMA on this port (THC_M_PRT_SWINT_CNT_1)
Touch Sequencer Frame Drop Counter for the 1st RXDMA (THC_M_PRT_FRAME_DROP_CNT_1)
THC Coaescing 1 (THC_M_PRT_COALESCE_1)
THC Read PRD Base Address Low for the 2nd RXDMA (THC_M_PRT_RPRD_BA_LOW_2)
THC Read PRD Base Address High for the 2nd RXDMA (THC_M_PRT_RPRD_BA_HI_2)
THC Read PRD Control for the 2nd RXDMA (THC_M_PRT_RPRD_CNTRL_2)
THC Read DMA Control for the 2nd RXDMA (THC_M_PRT_READ_DMA_CNTRL_2)
THC Read Interrupt Status for the 2nd RXDMA (THC_M_PRT_READ_DMA_INT_STS_2)
THC Read DMA Error Register for the 2nd RXDMA (THC_M_PRT_READ_DMA_ERR_2)
Touch Sequencer GuC Tail Offset Address Low for the 2nd RXDMA (THC_M_PRT_GUC_OFFSET_LOW_2)
Touch Sequencer GuC Tail Offset Address High for the 2nd RXDMA (THC_M_PRT_GUC_OFFSET_HI_2)
Touch Host Controller GuC Work Queue Item Size for the 2nd RXDMA (THC_M_PRT_GUC_WORKQ_ITEM_SZ_2)
Touch Host Controller GuC Control register for the 2nd RXDMA (THC_M_PRT_GUC_WORKQ_SZ_2)
Touch Sequencer Control for the 2nd DMA (THC_M_PRT_TSEQ_CNTRL_2)
Touch Sequencer GuC Doorbell Address Low for the 2nd RXDMA (THC_M_PRT_GUC_DB_ADDR_LOW_2)
Touch Sequencer GuC Doorbell Address High for the 2nd RXDMA (THC_M_PRT_GUC_DB_ADDR_HI_2)
Touch Sequencer GuC Doorbell Data for PRD2 (THC_M_PRT_GUC_DB_DATA_2)
Touch Sequencer GuC Tail Offset Initial Value for the 2nd RXDMA (THC_M_PRT_GUC_OFFSET_INITVAL_2)
THC Device Address for the bulk/touch data read for the 1st RXDMA (THC_M_PRT_RD_BULK_ADDR_2)
THC Gfx/SW Doorbell Count from the 2nd Stream RXDMA on this port (THC_M_PRT_DB_CNT_2)
THC Frame Count from the 2nd Stream RXDMA on this port (THC_M_PRT_FRM_CNT_2)
THC Micro Frame Count from the 2nd Stream RXDMA on this port (THC_M_PRT_UFRM_CNT_2)
THC Packet Count from the 2nd Stream RXDMA on this port (THC_M_PRT_RXDMA_PKT_CNT_2)
THC Software Interrupt Count from the 2nd Stream RXDMA on this port (THC_M_PRT_SWINT_CNT_2)
Touch Sequencer Frame Drop Counter for the 2nd RXDMA (THC_M_PRT_FRAME_DROP_CNT_2)
THC Coaescing 2 (THC_M_PRT_COALESCE_2)
THC PCI Configuration
THC PCI Configuration Device ID and Vendor ID (THC_CFG_DID_VID) Status and Command (THC_CFG_STS_CMD) Revision ID and Class Code (THC_CFG_CC_RID) BIST_Header Type_Latency Timer_Cache Line Size (THC_CFG_BIST_HTYPE_LT_CLS) THC BAR0 MMIO Low (THC_CFG_BAR0_LOW) THC BAR0 MMIO High (THC_CFG_BAR0_HI) Subsystem and Vendor ID (THC_CFG_SID_SVID) Capability List Pointer (THC_CFG_CAPP) Interrupt Configuration (THC_CFG_INT) THC Unsupported Request Status (THC_CFG_UR_STS_CTL) MSI Message Control_ Next Pointer and Capability ID (THC_CFG_MSIMC_MSINP_MSICID) MSI Message Address (THC_CFG_MSIMA) MSI Message Upper Address (THC_CFG_MSIMUA) MSI Message Data (THC_CFG_MSIMD) PCI Power Management Capability (THC_CFG_PMCAP_PMNP_PMCID) PCI Power Management Control and Status (THC_CFG_PMD_PMCSRBSE_PMCSR) Device Idle Capability (THC_CFG_DEVIDLE) Vendor Specific Header (THC_CFG_VSHDR) SW LTR Pointer Regsiter (THC_CFG_SWLTRPTR) Device Idle Pointer Register (THC_CFG_DEVIDLEPTR) Device Idle Power On Latency (THC_CFG_DEVIDLEPOL) Power Control Enables (THC_CFG_PCE)
Device ID and Vendor ID (THC_CFG_DID_VID)
Status and Command (THC_CFG_STS_CMD)
Revision ID and Class Code (THC_CFG_CC_RID)
BIST_Header Type_Latency Timer_Cache Line Size (THC_CFG_BIST_HTYPE_LT_CLS)
THC BAR0 MMIO Low (THC_CFG_BAR0_LOW)
THC BAR0 MMIO High (THC_CFG_BAR0_HI)
Subsystem and Vendor ID (THC_CFG_SID_SVID)
Capability List Pointer (THC_CFG_CAPP)
Interrupt Configuration (THC_CFG_INT)
THC Unsupported Request Status (THC_CFG_UR_STS_CTL)
MSI Message Control_ Next Pointer and Capability ID (THC_CFG_MSIMC_MSINP_MSICID)
MSI Message Address (THC_CFG_MSIMA)
MSI Message Upper Address (THC_CFG_MSIMUA)
MSI Message Data (THC_CFG_MSIMD)
PCI Power Management Capability (THC_CFG_PMCAP_PMNP_PMCID)
PCI Power Management Control and Status (THC_CFG_PMD_PMCSRBSE_PMCSR)
Device Idle Capability (THC_CFG_DEVIDLE)
Vendor Specific Header (THC_CFG_VSHDR)
SW LTR Pointer Regsiter (THC_CFG_SWLTRPTR)
Device Idle Pointer Register (THC_CFG_DEVIDLEPTR)
Device Idle Power On Latency (THC_CFG_DEVIDLEPOL)
Power Control Enables (THC_CFG_PCE)
UART Additional MMIO
UART Additional MMIO Clock Configuration (CLOCKS) Resets (RESETS) Active LTR (ACTIVELTR_VALUE) Idle LTR (IDLELTR_VALUE) Tx Byte Count (TX_BYTE_COUNT) Rx Byte Count (RX_BYTE_COUNT) Scratchpad Register 0 (SW_SCRATCH_0) Scratchpad Register 1 (SW_SCRATCH_1) Scratchpad Register 2 (SW_SCRATCH_2) Scratchpad Register 3 (SW_SCRATCH_3) Clock Gate (CLOCK_GATE) Address Low (REMAP_ADDR_LO) Address High (REMAP_ADDR_HI) Device Idle Control (DEVIDLE_CONTROL) Capabilities (CAPABLITIES)
Clock Configuration (CLOCKS)
Resets (RESETS)
Active LTR (ACTIVELTR_VALUE)
Idle LTR (IDLELTR_VALUE)
Tx Byte Count (TX_BYTE_COUNT)
Rx Byte Count (RX_BYTE_COUNT)
Scratchpad Register 0 (SW_SCRATCH_0)
Scratchpad Register 1 (SW_SCRATCH_1)
Scratchpad Register 2 (SW_SCRATCH_2)
Scratchpad Register 3 (SW_SCRATCH_3)
Clock Gate (CLOCK_GATE)
Address Low (REMAP_ADDR_LO)
Address High (REMAP_ADDR_HI)
Device Idle Control (DEVIDLE_CONTROL)
Capabilities (CAPABLITIES)
UART DMA
UART DMA DMA Transfer Source Address Low 0 (SAR_LO0) DMA Transfer Source Address High 0 (SAR_HI0) DMA Transfer Destination Address Low 0 (DAR_LO0) DMA Transfer Destination Address High 0 (DAR_HI0) Linked List Pointer Low 0 (LLP_LO0) Linked List Pointer High 0 (LLP_HI0) Control Register Low 0 (CTL_LO0) Control Register High 0 (CTL_HI0) Source Status 0 (SSTAT0) Destination Status 0 (DSTAT0) Source Status Address Low 0 (SSTATAR_LO0) Source Status Address High 0 (SSTATAR_HI0) Destination Status Address Low 0 (DSTATAR_LO0) Destination Status Address High 0 (DSTATAR_HI0) DMA Transfer Configuration Low 0 (CFG_LO0) DMA Transfer Configuration High 0 (CFG_HI0) Source Gather 0 (SGR0) Destination Scatter 0 (DSR0) DMA Transfer Source Address Low 1 (SAR_LO1) DMA Transfer Source Address High 1 (SAR_HI1) DMA Transfer Destination Address Low 1 (DAR_LO1) DMA Transfer Destination Address High 1 (DAR_HI1) Linked List Pointer Low 1 (LLP_LO1) Linked List Pointer High 1 (LLP_HI1) Control Register Low 1 (CTL_LO1) Control Register High 1 (CTL_HI1) Source Status 1 (SSTAT1) Destination Status 1 (DSTAT1) Source Status Address Low 1 (SSTATAR_LO1) Source Status Address High 1 (SSTATAR_HI1) Destination Status Address Low 1 (DSTATAR_LO1) Destination Status Address High 1 (DSTATAR_HI1) DMA Transfer Configuration Low 1 (CFG_LO1) DMA Transfer Configuration High 1 (CFG_HI1) Source Gather 1 (SGR1) Destination Scatter 1 (DSR1) Raw Interrupt Status (RawTfr) Raw Status for Block Interrupts (RawBlock) Raw Status for Source Transaction Interrupts (RawSrcTran) Raw Status for Destination Transaction Interrupts (RawDstTran) Raw Status for Error Interrupts (RawErr) Status for Transfer Interrupts (StatusTfr) Status for Block Interrupts (StatusBlock) Status for Source Transaction Interrupts (StatusSrcTran) Status for Destination Transaction Interrupts (StatusDstTran) Status for Error Interrupts (StatusErr) Mask for Transfer Interrupts (MaskTfr) Mask for Block Interrupts (MaskBlock) Mask for Source Transaction Interrupts (MaskSrcTran) Mask for Destination Transaction Interrupts (MaskDstTran) Mask for Error Interrupts (MaskErr) Clear for Transfer Interrupts (ClearTfr) Clear for Block Interrupts (ClearBlock) Clear for Source Transaction Interrupts (ClearSrcTran) Clear for Destination Transaction Interrupts (ClearDstTran) Clear for Error Interrupts (ClearErr) Combined Status (StatusInt) DMA Configuration (DmaCfgReg) DMA Channel Enable (ChEnReg) Global DMA Configuration (GLOBAL_CFG)
DMA Transfer Source Address Low 0 (SAR_LO0)
DMA Transfer Source Address High 0 (SAR_HI0)
DMA Transfer Destination Address Low 0 (DAR_LO0)
DMA Transfer Destination Address High 0 (DAR_HI0)
Linked List Pointer Low 0 (LLP_LO0)
Linked List Pointer High 0 (LLP_HI0)
Control Register Low 0 (CTL_LO0)
Control Register High 0 (CTL_HI0)
Source Status 0 (SSTAT0)
Destination Status 0 (DSTAT0)
Source Status Address Low 0 (SSTATAR_LO0)
Source Status Address High 0 (SSTATAR_HI0)
Destination Status Address Low 0 (DSTATAR_LO0)
Destination Status Address High 0 (DSTATAR_HI0)
DMA Transfer Configuration Low 0 (CFG_LO0)
DMA Transfer Configuration High 0 (CFG_HI0)
Source Gather 0 (SGR0)
Destination Scatter 0 (DSR0)
DMA Transfer Source Address Low 1 (SAR_LO1)
DMA Transfer Source Address High 1 (SAR_HI1)
DMA Transfer Destination Address Low 1 (DAR_LO1)
DMA Transfer Destination Address High 1 (DAR_HI1)
Linked List Pointer Low 1 (LLP_LO1)
Linked List Pointer High 1 (LLP_HI1)
Control Register Low 1 (CTL_LO1)
Control Register High 1 (CTL_HI1)
Source Status 1 (SSTAT1)
Destination Status 1 (DSTAT1)
Source Status Address Low 1 (SSTATAR_LO1)
Source Status Address High 1 (SSTATAR_HI1)
Destination Status Address Low 1 (DSTATAR_LO1)
Destination Status Address High 1 (DSTATAR_HI1)
DMA Transfer Configuration Low 1 (CFG_LO1)
DMA Transfer Configuration High 1 (CFG_HI1)
Source Gather 1 (SGR1)
Destination Scatter 1 (DSR1)
Raw Interrupt Status (RawTfr)
Raw Status for Block Interrupts (RawBlock)
Raw Status for Source Transaction Interrupts (RawSrcTran)
Raw Status for Destination Transaction Interrupts (RawDstTran)
Raw Status for Error Interrupts (RawErr)
Status for Transfer Interrupts (StatusTfr)
Status for Block Interrupts (StatusBlock)
Status for Source Transaction Interrupts (StatusSrcTran)
Status for Destination Transaction Interrupts (StatusDstTran)
Status for Error Interrupts (StatusErr)
Mask for Transfer Interrupts (MaskTfr)
Mask for Block Interrupts (MaskBlock)
Mask for Source Transaction Interrupts (MaskSrcTran)
Mask for Destination Transaction Interrupts (MaskDstTran)
Mask for Error Interrupts (MaskErr)
Clear for Transfer Interrupts (ClearTfr)
Clear for Block Interrupts (ClearBlock)
Clear for Source Transaction Interrupts (ClearSrcTran)
Clear for Destination Transaction Interrupts (ClearDstTran)
Clear for Error Interrupts (ClearErr)
Combined Status (StatusInt)
DMA Configuration (DmaCfgReg)
DMA Channel Enable (ChEnReg)
Global DMA Configuration (GLOBAL_CFG)
UART MMIO
UART MMIO Divisor Latch Low (DLL) Transmit Holding (THR) Receive Buffer (RBR) Interrupt Enable (IER) Divisor Latch High (DLH) FIFO Control (FCR) Interrupt Control (IIR) Line Control Register (LCR) Modem Control Register (MCR) Line Status Register (LSR) Modem Status Register (MSR) Scratchpad Register (SCR) Shadow Receive Buffer Register and Shadow Transmit Holding Register 0 (SRBR_STHR0) Shadow Receive Buffer Register and Shadow Transmit Holding Register 1 (SRBR_STHR1) Shadow Receive Buffer Register and Shadow Transmit Holding Register 2 (SRBR_STHR2) Shadow Receive Buffer Register and Shadow Transmit Holding Register 3 (SRBR_STHR3) Shadow Receive Buffer Register and Shadow Transmit Holding Register 4 (SRBR_STHR4) Shadow Receive Buffer Register and Shadow Transmit Holding Register 5 (SRBR_STHR5) Shadow Receive Buffer Register and Shadow Transmit Holding Register 6 (SRBR_STHR6) Shadow Receive Buffer Register and Shadow Transmit Holding Register 7 (SRBR_STHR7) Shadow Receive Buffer Register and Shadow Transmit Holding Register 8 (SRBR_STHR8) Shadow Receive Buffer Register and Shadow Transmit Holding Register 9 (SRBR_STHR9) Shadow Receive Buffer Register and Shadow Transmit Holding Register 10 (SRBR_STHR10) Shadow Receive Buffer Register and Shadow Transmit Holding Register 11 (SRBR_STHR11) Shadow Receive Buffer Register and Shadow Transmit Holding Register 12 (SRBR_STHR12) Shadow Receive Buffer Register and Shadow Transmit Holding Register 13 (SRBR_STHR13) Shadow Receive Buffer Register and Shadow Transmit Holding Register 14 (SRBR_STHR14) Shadow Receive Buffer Register and Shadow Transmit Holding Register 15 (SRBR_STHR15) FIFO Access Register (FAR) Transmit FIFO Read (TFR) Receive FIFO Write (RFW) UART Status Register (USR) Transmit FIFO Level (TFL) Receive FIFO Level (RFL) Software Reset Register (SRR) Shadow Request to Send (SRTS) Shadow Break Control Bit (SBCR) Shadow DMA Mode (SDMAM) Shadow FIFO Enable (SFE) Shadow RCVR Trigger (SRT) Shadow TX Empty Trigger. (STET) Halt TX (HTX) DMA Software Acknowledge (DMASA) Component Parameter Register (CPR) UART Component Version (UCV) Component Type Register (CTR)
Divisor Latch Low (DLL)
Transmit Holding (THR)
Receive Buffer (RBR)
Interrupt Enable (IER)
Divisor Latch High (DLH)
FIFO Control (FCR)
Interrupt Control (IIR)
Line Control Register (LCR)
Modem Control Register (MCR)
Line Status Register (LSR)
Modem Status Register (MSR)
Scratchpad Register (SCR)
Shadow Receive Buffer Register and Shadow Transmit Holding Register 0 (SRBR_STHR0)
Shadow Receive Buffer Register and Shadow Transmit Holding Register 1 (SRBR_STHR1)
Shadow Receive Buffer Register and Shadow Transmit Holding Register 2 (SRBR_STHR2)
Shadow Receive Buffer Register and Shadow Transmit Holding Register 3 (SRBR_STHR3)
Shadow Receive Buffer Register and Shadow Transmit Holding Register 4 (SRBR_STHR4)
Shadow Receive Buffer Register and Shadow Transmit Holding Register 5 (SRBR_STHR5)
Shadow Receive Buffer Register and Shadow Transmit Holding Register 6 (SRBR_STHR6)
Shadow Receive Buffer Register and Shadow Transmit Holding Register 7 (SRBR_STHR7)
Shadow Receive Buffer Register and Shadow Transmit Holding Register 8 (SRBR_STHR8)
Shadow Receive Buffer Register and Shadow Transmit Holding Register 9 (SRBR_STHR9)
Shadow Receive Buffer Register and Shadow Transmit Holding Register 10 (SRBR_STHR10)
Shadow Receive Buffer Register and Shadow Transmit Holding Register 11 (SRBR_STHR11)
Shadow Receive Buffer Register and Shadow Transmit Holding Register 12 (SRBR_STHR12)
Shadow Receive Buffer Register and Shadow Transmit Holding Register 13 (SRBR_STHR13)
Shadow Receive Buffer Register and Shadow Transmit Holding Register 14 (SRBR_STHR14)
Shadow Receive Buffer Register and Shadow Transmit Holding Register 15 (SRBR_STHR15)
FIFO Access Register (FAR)
Transmit FIFO Read (TFR)
Receive FIFO Write (RFW)
UART Status Register (USR)
Transmit FIFO Level (TFL)
Receive FIFO Level (RFL)
Software Reset Register (SRR)
Shadow Request to Send (SRTS)
Shadow Break Control Bit (SBCR)
Shadow DMA Mode (SDMAM)
Shadow FIFO Enable (SFE)
Shadow RCVR Trigger (SRT)
Shadow TX Empty Trigger. (STET)
Halt TX (HTX)
DMA Software Acknowledge (DMASA)
Component Parameter Register (CPR)
UART Component Version (UCV)
Component Type Register (CTR)
UART PCI Configuration
UART PCI Configuration Device Id And Vendor Id Register (DEVVENDID) Status And Command (STATUSCOMMAND) Revision Id And Class Code (REVCLASSCODE) Cache Line Latency Header And Bist (CLLATHEADERBIST) Base Address Register (BAR) Base Address Register High (BAR_HIGH) Base Address Register1 (BAR1) Base Address Register1 High (BAR1_HIGH) Subsystem Vendor And Subsystem Id (SUBSYSTEMID) Expansion Rom Base Address (EXPANSION_ROM_BASEADDR) Capabilities Pointer Register (CAPABILITYPTR) Interrupt Register (INTERRUPTREG) Power Management Capability Id (POWERCAPID) Power Management Control And Status Register (PMECTRLSTATUS) Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD) Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG) Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG) Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG) D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG) General Purpose Read Write Register1 (GEN_REGRW1) General Purpose Read Write Register2 (GEN_REGRW2) General Purpose Read Write Register3 (GEN_REGRW3) General Purpose Read Write Register4 (GEN_REGRW4) General Purpose Input Register (GEN_INPUT_REG)
Device Id And Vendor Id Register (DEVVENDID)
Status And Command (STATUSCOMMAND)
Revision Id And Class Code (REVCLASSCODE)
Cache Line Latency Header And Bist (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Subsystem Vendor And Subsystem Id (SUBSYSTEMID)
Expansion Rom Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer Register (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Capability Id (POWERCAPID)
Power Management Control And Status Register (PMECTRLSTATUS)
Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD)
Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG)
Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG)
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write Register1 (GEN_REGRW1)
General Purpose Read Write Register2 (GEN_REGRW2)
General Purpose Read Write Register3 (GEN_REGRW3)
General Purpose Read Write Register4 (GEN_REGRW4)
General Purpose Input Register (GEN_INPUT_REG)
USB MMIO
USB MMIO Capability Registers Length (CAPLENGTH) Host Controller Interface Version Number (HCIVERSION) Structural Parameters 1 (HCSPARAMS1) Structural Parameters 2 (HCSPARAMS2) Structural Parameters 3 (HCSPARAMS3) Capability Parameters (HCCPARAMS) Doorbell Offset (DBOFF) Runtime Register Space Offset (RTSOFF) USB Command (USBCMD) USB Status (USBSTS) Page Size (PAGESIZE) Device Notification Control (DNCTRL) Command Ring Low (CRCR_LO) Command Ring High (CRCR_HI) Device Context Base Address Array Pointer Low (DCBAAP_LO) Device Context Base Address Array Pointer High (DCBAAP_HI) Configure Reg (CONFIG) Port Status AndControl USB2 (PORTSC1) Port Power Management Status Aand Control USB2 (PORTPMSC1) Port X Hardware LPM Control Register (PORTHLPMC1) Port Status AndControl USB2 (PORTSC2) Port Power Management Status Aand Control USB2 (PORTPMSC2) Port X Hardware LPM Control Register (PORTHLPMC2) Port Status AndControl USB2 (PORTSC3) Port Power Management Status Aand Control USB2 (PORTPMSC3) Port X Hardware LPM Control Register (PORTHLPMC3) Port Status AndControl USB2 (PORTSC4) Port Power Management Status Aand Control USB2 (PORTPMSC4) Port X Hardware LPM Control Register (PORTHLPMC4) Port Status AndControl USB2 (PORTSC5) Port Power Management Status Aand Control USB2 (PORTPMSC5) Port X Hardware LPM Control Register (PORTHLPMC5) Port Status AndControl USB2 (PORTSC6) Port Power Management Status Aand Control USB2 (PORTPMSC6) Port X Hardware LPM Control Register (PORTHLPMC6) Port Status AndControl USB2 (PORTSC7) Port Power Management Status Aand Control USB2 (PORTPMSC7) Port X Hardware LPM Control Register (PORTHLPMC7) Port Status AndControl USB2 (PORTSC8) Port Power Management Status Aand Control USB2 (PORTPMSC8) Port X Hardware LPM Control Register (PORTHLPMC8) Port Status And Control USB2 (PORTSC9) Port Power Management Status Aand Control USB2 (PORTPMSC9) Port X Hardware LPM Control Register (PORTHLPMC9) Port Status AndControl USB2 (PORTSC10) Port Power Management Status Aand Control USB2 (PORTPMSC10) Port X Hardware LPM Control Register (PORTHLPMC10) Port Status AndControl USB2 (PORTSC11) Port Power Management Status Aand Control USB2 (PORTPMSC11) Port X Hardware LPM Control Register (PORTHLPMC11) Port Status AndControl USB2 (PORTSC12) Port Power Management Status Aand Control USB2 (PORTPMSC12) Port X Hardware LPM Control Register (PORTHLPMC12) Port Status AndControl USB2 (PORTSC13) Port Power Management Status Aand Control USB2 (PORTPMSC13) Port X Hardware LPM Control Register (PORTHLPMC13) Port Status AndControl USB2 (PORTSC14) Port Power Management Status Aand Control USB2 (PORTPMSC14) Port X Hardware LPM Control Register (PORTHLPMC14) Port Status And Control USB3 (PORTSC17) Port Power Management Status And Control USB3 (PORTPMSC17) USB3 Port Link Info (PORTLI17) PORT SOFT ERR CNT (PORTSOFTERRX17) Port Status And Control USB3 (PORTSC18) Port Power Management Status And Control USB3 (PORTPMSC18) USB3 Port Link Info (PORTLI18) Port Status And Control USB3 (PORTSC19) Port Power Management Status And Control USB3 (PORTPMSC19) USB3 Port Link Info (PORTLI19) Port Status And Control USB3 (PORTSC20) Port Power Management Status And Control USB3 (PORTPMSC20) USB3 Port Link Info (PORTLI20) Port Status And Control USB3 (PORTSC21) Port Power Management Status And Control USB3 (PORTPMSC21) USB3 Port Link Info (PORTLI21) Port Status And Control USB3 (PORTSC22) Port Power Management Status And Control USB3 (PORTPMSC22) USB3 Port Link Info (PORTLI22) Port Status And Control USB3 (PORTSC23) Port Power Management Status And Control USB3 (PORTPMSC23) USB3 Port Link Info (PORTLI23) Port Status And Control USB3 (PORTSC24) Port Power Management Status And Control USB3 (PORTPMSC24) USB3 Port Link Info (PORTLI24) Port Status And Control USB3 (PORTSC25) Port Power Management Status And Control USB3 (PORTPMSC25) USB3 Port Link Info (PORTLI25) Port Status And Control USB3 (PORTSC26) Port Power Management Status And Control USB3 (PORTPMSC26) USB3 Port Link Info (PORTLI26) Microframe Index (RTMFINDEX) Interrupter Management (IMAN0) Interrupter Moderation (IMOD0) Event Ring Segment Table Size (ERSTSZ0) Event Ring Segment Table Base Address Low (ERSTBA_LO0) Event Ring Segment Table Base Address High (ERSTBA_HI0) Event Ring Dequeue Pointer Low (ERDP_LO0) Event Ring Dequeue Pointer High (ERDP_HI0) Interrupter Management (IMAN1) Interrupter Moderation (IMOD1) Event Ring Segment Table Size (ERSTSZ1) Event Ring Segment Table Base Address Low (ERSTBA_LO1) Event Ring Segment Table Base Address High (ERSTBA_HI1) Event Ring Dequeue Pointer Low (ERDP_LO1) Event Ring Dequeue Pointer High (ERDP_HI1) Interrupter Management (IMAN2) Interrupter Moderation (IMOD2) Event Ring Segment Table Size (ERSTSZ2) Event Ring Segment Table Base Address Low (ERSTBA_LO2) Event Ring Segment Table Base Address High (ERSTBA_HI2) Event Ring Dequeue Pointer Low (ERDP_LO2) Event Ring Dequeue Pointer High (ERDP_HI2) Interrupter Management (IMAN3) Interrupter Moderation (IMOD3) Event Ring Segment Table Size (ERSTSZ3) Event Ring Segment Table Base Address Low (ERSTBA_LO3) Event Ring Segment Table Base Address High (ERSTBA_HI3) Event Ring Dequeue Pointer Low (ERDP_LO3) Event Ring Dequeue Pointer High (ERDP_HI3) Interrupter Management (IMAN4) Interrupter Moderation (IMOD4) Event Ring Segment Table Size (ERSTSZ4) Event Ring Segment Table Base Address Low (ERSTBA_LO4) Event Ring Segment Table Base Address High (ERSTBA_HI4) Event Ring Dequeue Pointer Low (ERDP_LO4) Event Ring Dequeue Pointer High (ERDP_HI4) Interrupter Management (IMAN5) Interrupter Moderation (IMOD5) Event Ring Segment Table Size (ERSTSZ5) Event Ring Segment Table Base Address Low (ERSTBA_LO5) Event Ring Segment Table Base Address High (ERSTBA_HI5) Event Ring Dequeue Pointer Low (ERDP_LO5) Event Ring Dequeue Pointer High (ERDP_HI5) Interrupter Management (IMAN6) Interrupter Moderation (IMOD6) Event Ring Segment Table Size (ERSTSZ6) Event Ring Segment Table Base Address Low (ERSTBA_LO6) Event Ring Segment Table Base Address High (ERSTBA_HI6) Event Ring Dequeue Pointer Low (ERDP_LO6) Event Ring Dequeue Pointer High (ERDP_HI6) Interrupter Management (IMAN7) Interrupter Moderation (IMOD7) Event Ring Segment Table Size (ERSTSZ7) Event Ring Segment Table Base Address Low (ERSTBA_LO7) Event Ring Segment Table Base Address High (ERSTBA_HI7) Event Ring Dequeue Pointer Low (ERDP_LO7) Event Ring Dequeue Pointer High (ERDP_HI7) Door Bell (DB0) Door Bell (DB1) Door Bell (DB2) Door Bell (DB3) Door Bell (DB4) Door Bell (DB5) Door Bell (DB6) Door Bell (DB7) Door Bell (DB8) Door Bell (DB9) Door Bell (DB10) Door Bell (DB11) Door Bell (DB12) Door Bell (DB13) Door Bell (DB14) Door Bell (DB15) Door Bell (DB16) Door Bell (DB17) Door Bell (DB18) Door Bell (DB19) Door Bell (DB20) Door Bell (DB21) Door Bell (DB22) Door Bell (DB23) Door Bell (DB30) Door Bell (DB31) XECP SUPP USB2_1 (XECP_SUPP_USB2_1) XECP SUPP USB3_3 (XECP_SUPP_USB2_3) XECP SUPP USB2_4 Full Speed (XECP_SUPP_USB2_4) XECP_SUPP USB2_5 Low Speed (XECP_SUPP_USB2_5) XECP SUPP USB2_6 High Speed (XECP_SUPP_USB2_6) XECP SUPP USB3_0 (XECP_SUPP_USB3_0) XECP SUPP USB3_1 (XECP_SUPP_USB3_1) XECP SUPP USB3_2 (XECP_SUPP_USB3_2) XECP SUPP USB3_3 (XECP_SUPP_USB3_3) XECP SUPP USB3_4 (XECP_SUPP_USB3_4) XECP SUPP USB3_5 (XECP_SUPP_USB3_5) XECP SUPP USB3_6 (XECP_SUPP_USB3_6) XECP SUPP USB3_7 (XECP_SUPP_USB3_7) Host Control Scheduler (HOST_CTRL_SCH_REG) Power Management Control (PMCTRL_REG) Host Controller Misc Reg (HOST_CTRL_MISC_REG) Super Speed Port Enable (SSPE_REG) AUX Power Management Control (AUX_CTRL_REG1) SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG) USB2 Port Link Control 1 (USB2_LINK_MGR_CTRL_REG1) USB2 Port Link Control 2 (USB2_LINK_MGR_CTRL_REG2) USB2 Port Link Control 3 (USB2_LINK_MGR_CTRL_REG3) USB2 Port Link Control 4 (USB2_LINK_MGR_CTRL_REG4) Power Scheduler Control-0 (PWR_SCHED_CTRL0) Power Scheduler Control-1 (PWR_SCHED_CTRL2) AUX Power Management Control (AUX_CTRL_REG2) USB2 PHY Power Management Control (USB2_PHY_PMC) XHCI Aux Clock Control Register (XHCI_AUX_CCR) XHC Latency Tolerance Parameters LTV Control (XLTP_LTV1) XHC Latency Tolerance Parameters High Idle Time Control (XLTP_HITC) XHC Latency Tolerance Parameters Medium Idle Time Control (XLTP_MITC) XHC Latency Tolerance Parameters Low Idle Time Control (XLTP_LITC) LFPS On Count (LFPSONCOUNT_REG) USB2 Power Management Control (USB2PMCTRL_REG) USB Legacy Support Capability (USBLEGSUP) USB Legacy Support Control Status (USBLEGCTLSTS) Port Disable Override Capability Register (PDO_CAPABILITY) USB 2.0 Port Disable Override (USB2PDO) USB 3.0 Port Disable Override (USB3PDO) Command Reg (CMD_MMIO) Device Status (STS_MMIO) Revision ID (RID_MMIO) Programming Interface (PI_MMIO) Sub Class Code (SCC_MMIO) Base Class Code (BCC_MMIO) Cache Line Size (CLS_MMIO) Master Latency Timer (MLT_MMIO) Header Type (HT_MMIO) Memory Base Address (MBAR_MMIO) USB Subsystem Vendor ID (SSVID_MMIO) USB Subsystem ID (SSID_MMIO) Capabilities Pointer (CAP_PTR_MMIO) Interrupt Line (ILINE_MMIO) Interrupt Pin (IPIN_MMIO) Serial Bus Release Number (SBRN_MMIO) Frame Length Adjustment (FLADJ_MMIO) Best Effort Service Latency (BESL_MMIO) PCI Power Management Capability ID (PM_CID_MMIO) Next Item Pointer 1 (PM_NEXT_MMIO) Power Management Capabilities (PM_CAP_MMIO) Power Management Control/Status (PM_CS_MMIO) Message Signaled Interrupt CID (MSI_CID_MMIO) Next Item Pointer (MSI_NEXT_MMIO) Message Signaled Interrupt Message Control (MSI_MCTL_MMIO) Message Signaled Interrupt Message Address (MSI_MAD_MMIO) Message Signaled Interrupt Upper Address (MSI_MUAD_MMIO) Message Signaled Interrupt Message Data (MSI_MD_MMIO) DAP USB 2.0 Port <N> Control 0 (DAP_USB2_PORT_CONTROL_0_REG_0_MMIO) DAP USB 2.0 Port <N> Control 1 (DAP_USB2_PORT_CONTROL_1_REG_0_MMIO) DAP USB 2.0 Port <N> Status (DAP_USB2_PORT_STATUS_REG_0_MMIO) DAP USB 3.0 Port <N> Control 0 (DAP_ESS_PORT_CONTROL_0_REG_0_MMIO) DAP USB 3.0 Port <N> Control 1 (DAP_ESS_PORT_CONTROL_1_REG_0_MMIO) DAP USB 3.0 Port <N> Status (DAP_ESS_PORT_STATUS_REG_0_MMIO) GLOBAL TIME SYNC CAP REG (GLOBAL_TIME_SYNC_CAP_REG) GLOBAL TIME SYNC CTRL REG (GLOBAL_TIME_SYNC_CTRL_REG) MICROFRAME TIME REG (MICROFRAME_TIME_REG) Global Time Value (Low Register) (GLOBAL_TIME_LOW_REG) GLOBAL TIME HI REG (GLOBAL_TIME_HI_REG) XHCI USB2 Overcurrent Pin Mapping (U2OCM1) XHCI USB2 Overcurrent Pin Mapping (U2OCM2) XHCI USB2 Overcurrent Pin Mapping (U2OCM3) XHCI USB2 Overcurrent Pin Mapping (U2OCM4) XHCI USB2 Overcurrent Pin Mapping (U2OCM5) XHCI USB2 Overcurrent Pin Mapping (U2OCM6) XHCI USB2 Overcurrent Pin Mapping (U2OCM7) XHCI USB2 Overcurrent Pin Mapping (U2OCM8) XHCI USB2 Overcurrent Pin Mapping (U2OCM9) XHCI USB2 Overcurrent Pin Mapping (U2OCM10) XHCI USB2 Overcurrent Pin Mapping (U2OCM11) XHCI USB2 Overcurrent Pin Mapping (U2OCM12) XHCI USB3 Overcurrent Pin Mapping (U3OCM1) XHCI USB3 Overcurrent Pin Mapping (U3OCM2) XHCI USB3 Overcurrent Pin Mapping (U3OCM3) XHCI USB3 Overcurrent Pin Mapping (U3OCM4) XHCI USB3 Overcurrent Pin Mapping (U3OCM5) XHCI USB3 Overcurrent Pin Mapping (U3OCM6) XHCI USB3 Overcurrent Pin Mapping (U3OCM7) XHCI USB3 Overcurrent Pin Mapping (U3OCM8) XHCI USB3 Overcurrent Pin Mapping (U3OCM9) XHCI USB3 Overcurrent Pin Mapping (U3OCM10) XHCI USB3 Overcurrent Pin Mapping (U3OCM11) XHCI USB3 Overcurrent Pin Mapping (U3OCM12)
Capability Registers Length (CAPLENGTH)
Host Controller Interface Version Number (HCIVERSION)
Structural Parameters 1 (HCSPARAMS1)
Structural Parameters 2 (HCSPARAMS2)
Structural Parameters 3 (HCSPARAMS3)
Capability Parameters (HCCPARAMS)
Doorbell Offset (DBOFF)
Runtime Register Space Offset (RTSOFF)
USB Command (USBCMD)
USB Status (USBSTS)
Page Size (PAGESIZE)
Device Notification Control (DNCTRL)
Command Ring Low (CRCR_LO)
Command Ring High (CRCR_HI)
Device Context Base Address Array Pointer Low (DCBAAP_LO)
Device Context Base Address Array Pointer High (DCBAAP_HI)
Configure Reg (CONFIG)
Port Status AndControl USB2 (PORTSC1)
Port Power Management Status Aand Control USB2 (PORTPMSC1)
Port X Hardware LPM Control Register (PORTHLPMC1)
Port Status AndControl USB2 (PORTSC2)
Port Power Management Status Aand Control USB2 (PORTPMSC2)
Port X Hardware LPM Control Register (PORTHLPMC2)
Port Status AndControl USB2 (PORTSC3)
Port Power Management Status Aand Control USB2 (PORTPMSC3)
Port X Hardware LPM Control Register (PORTHLPMC3)
Port Status AndControl USB2 (PORTSC4)
Port Power Management Status Aand Control USB2 (PORTPMSC4)
Port X Hardware LPM Control Register (PORTHLPMC4)
Port Status AndControl USB2 (PORTSC5)
Port Power Management Status Aand Control USB2 (PORTPMSC5)
Port X Hardware LPM Control Register (PORTHLPMC5)
Port Status AndControl USB2 (PORTSC6)
Port Power Management Status Aand Control USB2 (PORTPMSC6)
Port X Hardware LPM Control Register (PORTHLPMC6)
Port Status AndControl USB2 (PORTSC7)
Port Power Management Status Aand Control USB2 (PORTPMSC7)
Port X Hardware LPM Control Register (PORTHLPMC7)
Port Status AndControl USB2 (PORTSC8)
Port Power Management Status Aand Control USB2 (PORTPMSC8)
Port X Hardware LPM Control Register (PORTHLPMC8)
Port Status And Control USB2 (PORTSC9)
Port Power Management Status Aand Control USB2 (PORTPMSC9)
Port X Hardware LPM Control Register (PORTHLPMC9)
Port Status AndControl USB2 (PORTSC10)
Port Power Management Status Aand Control USB2 (PORTPMSC10)
Port X Hardware LPM Control Register (PORTHLPMC10)
Port Status AndControl USB2 (PORTSC11)
Port Power Management Status Aand Control USB2 (PORTPMSC11)
Port X Hardware LPM Control Register (PORTHLPMC11)
Port Status AndControl USB2 (PORTSC12)
Port Power Management Status Aand Control USB2 (PORTPMSC12)
Port X Hardware LPM Control Register (PORTHLPMC12)
Port Status AndControl USB2 (PORTSC13)
Port Power Management Status Aand Control USB2 (PORTPMSC13)
Port X Hardware LPM Control Register (PORTHLPMC13)
Port Status AndControl USB2 (PORTSC14)
Port Power Management Status Aand Control USB2 (PORTPMSC14)
Port X Hardware LPM Control Register (PORTHLPMC14)
Port Status And Control USB3 (PORTSC17)
Port Power Management Status And Control USB3 (PORTPMSC17)
USB3 Port Link Info (PORTLI17)
PORT SOFT ERR CNT (PORTSOFTERRX17)
Port Status And Control USB3 (PORTSC18)
Port Power Management Status And Control USB3 (PORTPMSC18)
USB3 Port Link Info (PORTLI18)
Port Status And Control USB3 (PORTSC19)
Port Power Management Status And Control USB3 (PORTPMSC19)
USB3 Port Link Info (PORTLI19)
Port Status And Control USB3 (PORTSC20)
Port Power Management Status And Control USB3 (PORTPMSC20)
USB3 Port Link Info (PORTLI20)
Port Status And Control USB3 (PORTSC21)
Port Power Management Status And Control USB3 (PORTPMSC21)
USB3 Port Link Info (PORTLI21)
Port Status And Control USB3 (PORTSC22)
Port Power Management Status And Control USB3 (PORTPMSC22)
USB3 Port Link Info (PORTLI22)
Port Status And Control USB3 (PORTSC23)
Port Power Management Status And Control USB3 (PORTPMSC23)
USB3 Port Link Info (PORTLI23)
Port Status And Control USB3 (PORTSC24)
Port Power Management Status And Control USB3 (PORTPMSC24)
USB3 Port Link Info (PORTLI24)
Port Status And Control USB3 (PORTSC25)
Port Power Management Status And Control USB3 (PORTPMSC25)
USB3 Port Link Info (PORTLI25)
Port Status And Control USB3 (PORTSC26)
Port Power Management Status And Control USB3 (PORTPMSC26)
USB3 Port Link Info (PORTLI26)
Microframe Index (RTMFINDEX)
Interrupter Management (IMAN0)
Interrupter Moderation (IMOD0)
Event Ring Segment Table Size (ERSTSZ0)
Event Ring Segment Table Base Address Low (ERSTBA_LO0)
Event Ring Segment Table Base Address High (ERSTBA_HI0)
Event Ring Dequeue Pointer Low (ERDP_LO0)
Event Ring Dequeue Pointer High (ERDP_HI0)
Interrupter Management (IMAN1)
Interrupter Moderation (IMOD1)
Event Ring Segment Table Size (ERSTSZ1)
Event Ring Segment Table Base Address Low (ERSTBA_LO1)
Event Ring Segment Table Base Address High (ERSTBA_HI1)
Event Ring Dequeue Pointer Low (ERDP_LO1)
Event Ring Dequeue Pointer High (ERDP_HI1)
Interrupter Management (IMAN2)
Interrupter Moderation (IMOD2)
Event Ring Segment Table Size (ERSTSZ2)
Event Ring Segment Table Base Address Low (ERSTBA_LO2)
Event Ring Segment Table Base Address High (ERSTBA_HI2)
Event Ring Dequeue Pointer Low (ERDP_LO2)
Event Ring Dequeue Pointer High (ERDP_HI2)
Interrupter Management (IMAN3)
Interrupter Moderation (IMOD3)
Event Ring Segment Table Size (ERSTSZ3)
Event Ring Segment Table Base Address Low (ERSTBA_LO3)
Event Ring Segment Table Base Address High (ERSTBA_HI3)
Event Ring Dequeue Pointer Low (ERDP_LO3)
Event Ring Dequeue Pointer High (ERDP_HI3)
Interrupter Management (IMAN4)
Interrupter Moderation (IMOD4)
Event Ring Segment Table Size (ERSTSZ4)
Event Ring Segment Table Base Address Low (ERSTBA_LO4)
Event Ring Segment Table Base Address High (ERSTBA_HI4)
Event Ring Dequeue Pointer Low (ERDP_LO4)
Event Ring Dequeue Pointer High (ERDP_HI4)
Interrupter Management (IMAN5)
Interrupter Moderation (IMOD5)
Event Ring Segment Table Size (ERSTSZ5)
Event Ring Segment Table Base Address Low (ERSTBA_LO5)
Event Ring Segment Table Base Address High (ERSTBA_HI5)
Event Ring Dequeue Pointer Low (ERDP_LO5)
Event Ring Dequeue Pointer High (ERDP_HI5)
Interrupter Management (IMAN6)
Interrupter Moderation (IMOD6)
Event Ring Segment Table Size (ERSTSZ6)
Event Ring Segment Table Base Address Low (ERSTBA_LO6)
Event Ring Segment Table Base Address High (ERSTBA_HI6)
Event Ring Dequeue Pointer Low (ERDP_LO6)
Event Ring Dequeue Pointer High (ERDP_HI6)
Interrupter Management (IMAN7)
Interrupter Moderation (IMOD7)
Event Ring Segment Table Size (ERSTSZ7)
Event Ring Segment Table Base Address Low (ERSTBA_LO7)
Event Ring Segment Table Base Address High (ERSTBA_HI7)
Event Ring Dequeue Pointer Low (ERDP_LO7)
Event Ring Dequeue Pointer High (ERDP_HI7)
Door Bell (DB0)
Door Bell (DB1)
Door Bell (DB2)
Door Bell (DB3)
Door Bell (DB4)
Door Bell (DB5)
Door Bell (DB6)
Door Bell (DB7)
Door Bell (DB8)
Door Bell (DB9)
Door Bell (DB10)
Door Bell (DB11)
Door Bell (DB12)
Door Bell (DB13)
Door Bell (DB14)
Door Bell (DB15)
Door Bell (DB16)
Door Bell (DB17)
Door Bell (DB18)
Door Bell (DB19)
Door Bell (DB20)
Door Bell (DB21)
Door Bell (DB22)
Door Bell (DB23)
Door Bell (DB30)
Door Bell (DB31)
XECP SUPP USB2_1 (XECP_SUPP_USB2_1)
XECP SUPP USB3_3 (XECP_SUPP_USB2_3)
XECP SUPP USB2_4 Full Speed (XECP_SUPP_USB2_4)
XECP_SUPP USB2_5 Low Speed (XECP_SUPP_USB2_5)
XECP SUPP USB2_6 High Speed (XECP_SUPP_USB2_6)
XECP SUPP USB3_0 (XECP_SUPP_USB3_0)
XECP SUPP USB3_1 (XECP_SUPP_USB3_1)
XECP SUPP USB3_2 (XECP_SUPP_USB3_2)
XECP SUPP USB3_3 (XECP_SUPP_USB3_3)
XECP SUPP USB3_4 (XECP_SUPP_USB3_4)
XECP SUPP USB3_5 (XECP_SUPP_USB3_5)
XECP SUPP USB3_6 (XECP_SUPP_USB3_6)
XECP SUPP USB3_7 (XECP_SUPP_USB3_7)
Host Control Scheduler (HOST_CTRL_SCH_REG)
Power Management Control (PMCTRL_REG)
Host Controller Misc Reg (HOST_CTRL_MISC_REG)
Super Speed Port Enable (SSPE_REG)
AUX Power Management Control (AUX_CTRL_REG1)
SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG)
USB2 Port Link Control 1 (USB2_LINK_MGR_CTRL_REG1)
USB2 Port Link Control 2 (USB2_LINK_MGR_CTRL_REG2)
USB2 Port Link Control 3 (USB2_LINK_MGR_CTRL_REG3)
USB2 Port Link Control 4 (USB2_LINK_MGR_CTRL_REG4)
Power Scheduler Control-0 (PWR_SCHED_CTRL0)
Power Scheduler Control-1 (PWR_SCHED_CTRL2)
AUX Power Management Control (AUX_CTRL_REG2)
USB2 PHY Power Management Control (USB2_PHY_PMC)
XHCI Aux Clock Control Register (XHCI_AUX_CCR)
XHC Latency Tolerance Parameters LTV Control (XLTP_LTV1)
XHC Latency Tolerance Parameters High Idle Time Control (XLTP_HITC)
XHC Latency Tolerance Parameters Medium Idle Time Control (XLTP_MITC)
XHC Latency Tolerance Parameters Low Idle Time Control (XLTP_LITC)
LFPS On Count (LFPSONCOUNT_REG)
USB2 Power Management Control (USB2PMCTRL_REG)
USB Legacy Support Capability (USBLEGSUP)
USB Legacy Support Control Status (USBLEGCTLSTS)
Port Disable Override Capability Register (PDO_CAPABILITY)
USB 2.0 Port Disable Override (USB2PDO)
USB 3.0 Port Disable Override (USB3PDO)
Command Reg (CMD_MMIO)
Device Status (STS_MMIO)
Revision ID (RID_MMIO)
Programming Interface (PI_MMIO)
Sub Class Code (SCC_MMIO)
Base Class Code (BCC_MMIO)
Cache Line Size (CLS_MMIO)
Master Latency Timer (MLT_MMIO)
Header Type (HT_MMIO)
Memory Base Address (MBAR_MMIO)
USB Subsystem Vendor ID (SSVID_MMIO)
USB Subsystem ID (SSID_MMIO)
Capabilities Pointer (CAP_PTR_MMIO)
Interrupt Line (ILINE_MMIO)
Interrupt Pin (IPIN_MMIO)
Serial Bus Release Number (SBRN_MMIO)
Frame Length Adjustment (FLADJ_MMIO)
Best Effort Service Latency (BESL_MMIO)
PCI Power Management Capability ID (PM_CID_MMIO)
Next Item Pointer 1 (PM_NEXT_MMIO)
Power Management Capabilities (PM_CAP_MMIO)
Power Management Control/Status (PM_CS_MMIO)
Message Signaled Interrupt CID (MSI_CID_MMIO)
Next Item Pointer (MSI_NEXT_MMIO)
Message Signaled Interrupt Message Control (MSI_MCTL_MMIO)
Message Signaled Interrupt Message Address (MSI_MAD_MMIO)
Message Signaled Interrupt Upper Address (MSI_MUAD_MMIO)
Message Signaled Interrupt Message Data (MSI_MD_MMIO)
DAP USB 2.0 Port <N> Control 0 (DAP_USB2_PORT_CONTROL_0_REG_0_MMIO)
DAP USB 2.0 Port <N> Control 1 (DAP_USB2_PORT_CONTROL_1_REG_0_MMIO)
DAP USB 2.0 Port <N> Status (DAP_USB2_PORT_STATUS_REG_0_MMIO)
DAP USB 3.0 Port <N> Control 0 (DAP_ESS_PORT_CONTROL_0_REG_0_MMIO)
DAP USB 3.0 Port <N> Control 1 (DAP_ESS_PORT_CONTROL_1_REG_0_MMIO)
DAP USB 3.0 Port <N> Status (DAP_ESS_PORT_STATUS_REG_0_MMIO)
GLOBAL TIME SYNC CAP REG (GLOBAL_TIME_SYNC_CAP_REG)
GLOBAL TIME SYNC CTRL REG (GLOBAL_TIME_SYNC_CTRL_REG)
MICROFRAME TIME REG (MICROFRAME_TIME_REG)
Global Time Value (Low Register) (GLOBAL_TIME_LOW_REG)
GLOBAL TIME HI REG (GLOBAL_TIME_HI_REG)
XHCI USB2 Overcurrent Pin Mapping (U2OCM1)
XHCI USB2 Overcurrent Pin Mapping (U2OCM2)
XHCI USB2 Overcurrent Pin Mapping (U2OCM3)
XHCI USB2 Overcurrent Pin Mapping (U2OCM4)
XHCI USB2 Overcurrent Pin Mapping (U2OCM5)
XHCI USB2 Overcurrent Pin Mapping (U2OCM6)
XHCI USB2 Overcurrent Pin Mapping (U2OCM7)
XHCI USB2 Overcurrent Pin Mapping (U2OCM8)
XHCI USB2 Overcurrent Pin Mapping (U2OCM9)
XHCI USB2 Overcurrent Pin Mapping (U2OCM10)
XHCI USB2 Overcurrent Pin Mapping (U2OCM11)
XHCI USB2 Overcurrent Pin Mapping (U2OCM12)
XHCI USB3 Overcurrent Pin Mapping (U3OCM1)
XHCI USB3 Overcurrent Pin Mapping (U3OCM2)
XHCI USB3 Overcurrent Pin Mapping (U3OCM3)
XHCI USB3 Overcurrent Pin Mapping (U3OCM4)
XHCI USB3 Overcurrent Pin Mapping (U3OCM5)
XHCI USB3 Overcurrent Pin Mapping (U3OCM6)
XHCI USB3 Overcurrent Pin Mapping (U3OCM7)
XHCI USB3 Overcurrent Pin Mapping (U3OCM8)
XHCI USB3 Overcurrent Pin Mapping (U3OCM9)
XHCI USB3 Overcurrent Pin Mapping (U3OCM10)
XHCI USB3 Overcurrent Pin Mapping (U3OCM11)
XHCI USB3 Overcurrent Pin Mapping (U3OCM12)
USB PCI Configuration
USB PCI Configuration Vendor ID (VID) Device ID (DID) Command Reg (CMD) Device Status (STS) Revision ID (RID) Programming Interface (PI) Sub Class Code (SCC) Base Class Code (BCC) Cache Line Size (CLS) Master Latency Timer (MLT) Header Type (HT) Memory Base Address (MBAR) USB Subsystem Vendor ID (SSVID) USB Subsystem ID (SSID) Capabilities Pointer (CAP_PTR) Interrupt Line (ILINE) Interrupt Pin (IPIN) XHC System Bus Configuration 1 (XHCC1) XHC System Bus Configuration 2 (XHCC2) Clock Gating (XHCLKGTEN) Audio Time Synchronization (AUDSYNC) Serial Bus Release Number (SBRN) Frame Length Adjustment (FLADJ) Best Effort Service Latency (BESL) PCI Power Management Capability ID (PM_CID) Next Item Pointer 1 (PM_NEXT) Power Management Capabilities (PM_CAP) Power Management Control/Status (PM_CS) Message Signaled Interrupt CID (MSI_CID) Next Item Pointer (MSI_NEXT) Message Signaled Interrupt Message Control (MSI_MCTL) Message Signaled Interrupt Message Address (MSI_MAD) Message Signaled Interrupt Upper Address (MSI_MUAD) Message Signaled Interrupt Message Data (MSI_MD) High Speed Configuration 2 (HSCFG2)
Vendor ID (VID)
Device ID (DID)
Command Reg (CMD)
Device Status (STS)
Revision ID (RID)
Programming Interface (PI)
Sub Class Code (SCC)
Base Class Code (BCC)
Cache Line Size (CLS)
Master Latency Timer (MLT)
Header Type (HT)
Memory Base Address (MBAR)
USB Subsystem Vendor ID (SSVID)
USB Subsystem ID (SSID)
Capabilities Pointer (CAP_PTR)
Interrupt Line (ILINE)
Interrupt Pin (IPIN)
XHC System Bus Configuration 1 (XHCC1)
XHC System Bus Configuration 2 (XHCC2)
Clock Gating (XHCLKGTEN)
Audio Time Synchronization (AUDSYNC)
Serial Bus Release Number (SBRN)
Frame Length Adjustment (FLADJ)
Best Effort Service Latency (BESL)
PCI Power Management Capability ID (PM_CID)
Next Item Pointer 1 (PM_NEXT)
Power Management Capabilities (PM_CAP)
Power Management Control/Status (PM_CS)
Message Signaled Interrupt CID (MSI_CID)
Next Item Pointer (MSI_NEXT)
Message Signaled Interrupt Message Control (MSI_MCTL)
Message Signaled Interrupt Message Address (MSI_MAD)
Message Signaled Interrupt Upper Address (MSI_MUAD)
Message Signaled Interrupt Message Data (MSI_MD)
High Speed Configuration 2 (HSCFG2)
xDCI MMIO Device
xDCI MMIO Device Device Configuration (DCFG) Device Control (DCTL) Device Event Enable (DEVTEN) Device Status (DSTS) Device Generic Command Parameter (DGCMDPAR) Device Generic Command (DGCMD) Device Ative USB Endpoint Enable (DALEPENA) Device Physical Endpoint-n Command Parameter 2 (DEPCMDPAR2_0) Device Physical Endpoint-n Command Parameter 1 (DEPCMDPAR1_0) Device Physical Endpoint-n Command Parameter 0 (DEPCMDPAR0_0) Device Physical Endpoint-n Command (DEPCMD_0)
Device Configuration (DCFG)
Device Control (DCTL)
Device Event Enable (DEVTEN)
Device Status (DSTS)
Device Generic Command Parameter (DGCMDPAR)
Device Generic Command (DGCMD)
Device Ative USB Endpoint Enable (DALEPENA)
Device Physical Endpoint-n Command Parameter 2 (DEPCMDPAR2_0)
Device Physical Endpoint-n Command Parameter 1 (DEPCMDPAR1_0)
Device Physical Endpoint-n Command Parameter 0 (DEPCMDPAR0_0)
Device Physical Endpoint-n Command (DEPCMD_0)
xDCI MMIO Global
xDCI MMIO Global Global Bus Configuration 0 (GSBUSCFG0) Global Bus Configuration 1 (GSBUSCFG1) Global Tx Threshold Control (GTXTHRCFG) Global Rx Threshold Control (GRXTHRCFG) Global Core Control (GCTL) Global Status (GSTS) Bus Address Low (GBUSERRADDRLO) Bus Address High (GBUSERRADDRHI)
Global Bus Configuration 0 (GSBUSCFG0)
Global Bus Configuration 1 (GSBUSCFG1)
Global Tx Threshold Control (GTXTHRCFG)
Global Rx Threshold Control (GRXTHRCFG)
Global Core Control (GCTL)
Global Status (GSTS)
Bus Address Low (GBUSERRADDRLO)
Bus Address High (GBUSERRADDRHI)
xDCI PCI Configuration
xDCI PCI Configuration Device Id And Vendor Id Register (DEVVENDID) Status And Command (STATUSCOMMAND) Revision Id And Class Code (REVCLASSCODE) Cache Line Latency Header And Bist (CLLATHEADERBIST) Base Address Register (BAR) Base Address Register High (BAR_HIGH) Base Address Register1 (BAR1) Base Address Register1 High (BAR1_HIGH) Subsystem Vendor And Subsystem Id (SUBSYSTEMID) Expansion Rom Base Address (EXPANSION_ROM_BASEADDR) Capabilities Pointer Register (CAPABILITYPTR) Interrupt Register (INTERRUPTREG) Power Management Capability Id (POWERCAPID) Power Management Control And Status Register (PMECTRLSTATUS) Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD) Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG) Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG) Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG) D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)
Device Id And Vendor Id Register (DEVVENDID)
Status And Command (STATUSCOMMAND)
Revision Id And Class Code (REVCLASSCODE)
Cache Line Latency Header And Bist (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Subsystem Vendor And Subsystem Id (SUBSYSTEMID)
Expansion Rom Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer Register (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Capability Id (POWERCAPID)
Power Management Control And Status Register (PMECTRLSTATUS)
Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD)
Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG)
Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG)
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)

Immediate Command Status (ICS) – Offset 68

This register provides the status of the immediate command.

Bit Range

Default

Access

Field Name and Description

15:2

0h

RO

Reserved (RSVD0)

This is a Reserved Register

1

0h

RW/1C/V

Immediate Result Valid (IRV)

This bit is set to a 1 by hardware when a new response is latched into the IR register. This is a status flag indicating that software may read the response from the Immediate Response register.Software must clear this bit (by writing a one to it) before issuing a new command so that the software may determine when a new response has arrived.

0

0h

RW/V

Immediate Command Busy (ICB)

When this bit as read as a 0, it indicates that a new command may be issued using the Immediate Command mechanism. When this bit transitions from a 0 to a 1 (via software writing a 1), the controller issues the command currently stored in the Immediate Command register to the codec over the link. When the corresponding response is latched into the Immediate Response register, the controller hardware sets the IRV flag and clears the ICB bit back to 0. SW may write this bit to a 0 if the bit fails to return to 0 after a reasonable timeout period.Note: An Immediate Command must not be issued while the CORB/RIRB mechanism is operating, otherwise the responses conflict. This must be enforced by software.
DMA Position Lower Base Address (DPLBASE)