Input Stream Descriptor x Control (ISD0CTL_B0) – Offset 80 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Input Stream Descriptor x Control (ISD0CTL_B0) – Offset 80

This register provides the control of the input stream DMA.

Bit Range	Default	Access	Field Name and Description
7:6	0h	RO	Reserved (RSVD0) This is a Reserved Register
5	0h	RO	FIFO Limit Change (FIFOLC) Writing a 1 to this bit indicates a new update to the FIFOL register has been made. After the HW has completed sequencing into the new effective FIFO size, it will clear this bit. Not supported.
4	0h	RW	Descriptor Error Interrupt Enable (DEIE) Controls whether an interrupt is generated when the Descriptor Error Status (DESE) bit is set.
3	0h	RW	FIFO Error Interrupt Enable (FEIE) This bit controls whether the occurrence of a FIFO error (overrun for input, under-run for output) will cause an interrupt or not. If this bit is not set, bit 3 in the Status register will be set, but the interrupt will not occur. Either way, the samples will be dropped.
2	0h	RW	Interrupt On Completion Enable (IOCE) This bit controls whether or not an interrupt occurs when a buffer completes with the IOC bit set in its descriptor. If this bit is not set, bit 2 in the Status register will be set, but the interrupt will not occur.
1	0h	RW/V	Stream Run (RUN) When set to 1 the DMA engine associated with this stream will be enabled to transfer data between FIFO and main memory. The SSYNC bit must also be cleared in order for the DMA engine to run. For output streams, the cadence generator is reset whenever the RUN bit is set.When cleared to 0 the DMA engine associated with this stream will be disabled. Hardware will report a 0 in this bit when the DMA engine is actually stopped. Software must read a 0 from this bit before modifying related control registers or restarting the DMA engine.
0	0h	RW/V	Stream Reset (SRST) Writing a 1 causes the corresponding stream to be reset. The Stream Descriptor registers (except the SRST bit itself) and FIFOs for the corresponding stream are reset. After the stream hardware has completed sequencing into the reset state, it will report a 1 in this bit. Software must read a 1 from this bit to verify that the stream is in reset. Writing a 0 causes the corresponding stream to exit reset. When the stream hardware is ready to begin operation, it will report a 0 in this bit. Software must read a 0 from this bit before accessing any of the stream registers. The RUN bit must be cleared before SRST is asserted.