Input Stream Descriptor x FIFO Size (ISD0FIFOS) – Offset 90 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
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GSPI MMIO
GSPI PCI Configuration
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I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
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Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Input Stream Descriptor x FIFO Size (ISD0FIFOS) – Offset 90

This register reports the FIFO size of the input stream DMA.

Bit Range	Default	Access	Field Name and Description
15:0	0h	RW/V	FIFO Size (FIFOS) Indicates the maximum number of bytes that could be evicted by the controller at one time. This is the maximum number of bytes that may have been received into the HW buffer but not yet transferred out, and is also the maximum possible value that the PICB count will increase by at one time.The FIFO size is calculated based on the stream format programmed in ISDxFMT register, the min frame of buffering setting in EM3.ISBSMFA[1:0] field, and the minimum buffer size threshold setting in EM2.BSMT[1:0] field. As the default value is zero, SW must write to the ISDxFMT register to kick off the FIFO size calculation, and read back to find out the HW allocated FIFO size.

Bit Range

Default

Access

Field Name and Description

15:0

RW/V

FIFO Size (FIFOS)

Indicates the maximum number of bytes that could be evicted by the controller at one time. This is the maximum number of bytes that may have been received into the HW buffer but not yet transferred out, and is also the maximum possible value that the PICB count will increase by at one time.The FIFO size is calculated based on the stream format programmed in ISDxFMT register, the min frame of buffering setting in EM3.ISBSMFA[1:0] field, and the minimum buffer size threshold setting in EM2.BSMT[1:0] field. As the default value is zero, SW must write to the ISDxFMT register to kick off the FIFO size calculation, and read back to find out the HW allocated FIFO size.

Input Stream Descriptor x Format (ISD0FMT)

Input Stream Descriptor x FIFO Eviction Watermark (ISD0FIFOW) Input Stream Descriptor x Format (ISD0FMT)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Input Stream Descriptor x FIFO Size (ISD0FIFOS) – Offset 90