Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2
ID | Date | Version | Classification |
---|---|---|---|
834576 | 10/10/2024 | 001 | Public |
Integrated Sensor Hub (ISH) PCI Configuration Registers
The following registers are at Device 18:Function 0.
Offset | Size (Bytes) | Register Name (Register Symbol) | Scope | Default Value |
---|---|---|---|---|
0h | 4 | Package | XXXX0000h | |
4h | 4 | Package | 00100000h | |
8h | 4 | Package | 000000XXh | |
ch | 4 | Package | 00000000h | |
10h | 4 | Package | 00000000h | |
14h | 4 | Package | 00000000h | |
18h | 4 | Package | 00000000h | |
1ch | 4 | Package | 00000000h | |
2ch | 4 | Package | 00000000h | |
30h | 4 | Package | 00000000h | |
34h | 4 | Package | 00000080h | |
3ch | 4 | Package | 00000100h | |
40h | 4 | Package | 00920010h | |
80h | 4 | Package | 48030001h | |
84h | 4 | Power Management Control And Status Register (PMECTRLSTATUS) | Package | 00000008h |
90h | 4 | Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD) | Package | F0140009h |
94h | 4 | Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG) | Package | 01400010h |
98h | 4 | Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG) | Package | 00000000h |
9ch | 4 | Package | 00000000h | |
a0h | 4 | D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG) | Package | 00000800h |
b0h | 4 | Package | 00000000h | |
b4h | 4 | Package | 00000000h | |
b8h | 4 | Package | 00000000h | |
bch | 4 | Package | 00000000h | |
c0h | 4 | Package | 00000000h | |
c4h | 4 | Package | 00000011h | |
c8h | 4 | Package | 00000000h | |
cch | 4 | Package | 00000000h | |
d0h | 4 | Package | 01800005h | |
d4h | 4 | Package | 00000000h | |
d8h | 4 | Package | 00000000h | |
dch | 4 | Package | 00000000h | |
e0h | 4 | Package | 00000000h | |
e4h | 4 | Package | 00000000h | |
100h | 4 | Package | 00010018h | |
104h | 4 | Ltr Max Snoop Non Snoop Latency Register (MAX_LATENCY_REGISTER) | Package | 00000000h |