Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID Date Version Classification
834576 10/10/2024 001 Public
Document Table of Contents
CNVi WiFi* PCI Configuration Vendor and Device ID (VEN_DEV_ID) Device Command and Status (PCI_COM_STAT) Class Code and Revision ID (PCI_CLASS_CODE) Base Address Register BAR0 Low (BAR0) Base Address Register BAR0 High (BAR1) Sub System Identification (SUBSYS_ID) Capabilities Pointer (CAP_PTR) Interrupt (INTERRUPT) PCI Express Capabilities (GIO_CAP) Device Capabilities (GIO_DEV_CAP) Device Control Register (GIO_DEV) Device Control 2 (GIO_DEV_CAP_2) Device Control (GIO_DEV_2) MSIX Capability (MSIX_CAP_HEAD) MSIX Capability Structure (MSIX_TABLE_OFFSET) MSIX Capability Structure (MSIX_PBA_OFFSET) Power Management Capabilities (PMC) Power Management Capabilities (PMCSR) Capability ID and Message Control (MSI_MSG_CTRL) MSI Low Address (MSI_LOW_ADD) MSI High Address (MSI_HIGH_ADD) MSI Data (MSI_DATA) Uncorrectable Error Severity (UNCORRECT_ERR_SEV) CORRECT Error Status (CORRECT_ERR_STAT) CORRECT Error MASK (CORRECT_ERR_MASK) Advanced Error Capabilities and Control (ADVANCED_ERR_CAP) Header Log 1 (HEADER_LOG1) Header Log 2 (HEADER_LOG2) Header Log 3 (HEADER_LOG3) Header Log 4 (HEADER_LOG4) Device Serial Number Capability (GIO_SERIAL_CAP) Serial Number Low (GIO_SERIAL_LOW) Serial Number Upper (GIO_SERIAL_UP) L1 substates Extended Capability Header (L1PM_SUB_EXTND_CAP_HEAD) L1 Substates Capability (L1PM_SUB_CAP) L1 Substates Control (L1PM_SUB_CNTRL) L1 Substates Control 2 (L1PM_SUB_CNTRL2) Vendor Specific Capability Header (VEN_SPEC_CAP) Vendor Specific Extended Capability (VEN_SPEC_EXTND_CAP) SW LTR Pointer (LTP_PTR) DevIdle Pointer (DEV_IDLE_PTR) DevIdle Power on Latency (DEV_IDLE_PWR)
eSPI PCR eSPI Device Configuration Register and Link Control (SLV_CFG_REG_CTL) eSPI Device Configuration Register Data (SLV_CFG_REG_DATA) Peripheral Channel Error for ESPI Device 0 (PCERR_SLV0) Peripheral Channel Error for ESPI Second Device (PCERR_SLV1) Virtual Wire Channel Error for eSPI First Device (VWERR_SLV0) Virtual Wire Channel Error for eSPI Second Device (VWERR_SLV1) Flash Access Channel Error for eSPI First Device (FCERR_SLV0) Link Error for eSPI First Device (LNKERR_SLV0) Link Error for eSPI Second Device (LNKERR_SLV1) Generic GPIO upstream VW Enables for eSPI First Device (VWGPIO_IN_EN_SLV[0]) Generic GPIO upstream VW Enables for eSPI Second Device (VWGPIO_IN_EN_SLV[1]) Generic GPIO downstream VW Enables for eSPI First Device (VWGPIO_OUT_EN_SLV[0]) Generic GPIO Downstream VW Enables for eSPI Second Device (VWGPIO_OUT_EN_SLV[1]) Generic GPIO VW control (VWGPIO_CTL) Peripheral Channel Error for ESPI Third Device (PCERR_SLV_EXT[2]) Virtual Channel Error for ESPI Third Device (VWERR_SLV_EXT[2]) Link Error for ESPI Third Device (LNKERR_SLV_EXT[2]) Generic GPIO Upstream VW Enables for eSPI Third Device (VWGPIO_IN_EN_SLV_EXT[2]) Generic GPIO Downstream VW Enables for eSPI Third Device (VWGPIO_OUT_EN_SLV_EXT[2]) Peripheral Channel Error for ESPI Fourth Device (PCERR_SLV_EXT[3]) Virtual Channel Error for ESPI Fourth Device 3 (VWERR_SLV_EXT[3]) Link Error for ESPI Fourth Device (LNKERR_SLV_EXT[3]) Generic GPIO Upstream VW Enables for eSPI Fourth Device (VWGPIO_IN_EN_SLV_EXT[3]) Generic GPIO Downstream VW Enables for eSPI Fourth Device (VWGPIO_OUT_EN_SLV_EXT[3])
GPIO Commumity 0 Family Base Address (FAMBAR) Pad Base Address (PADBAR) Miscellaneous Configuration (MISCCFG) Pad Ownership (PAD_OWN_GPP_D_0) Pad Ownership (PAD_OWN_GPP_D_1) Pad Ownership (PAD_OWN_GPP_D_2) Pad Ownership (PAD_OWN_GPP_R_0) Pad Ownership (PAD_OWN_GPP_R_1) Pad Ownership (PAD_OWN_GPP_J_0) Pad Ownership (PAD_OWN_GPP_J_1) Pad Ownership (PAD_OWN_GPP_J_2) Pad Configuration Lock (PADCFGLOCK_GPP_D_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_D_0) Pad Configuration Lock (PADCFGLOCK_GPP_R_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_R_0) Pad Configuration Lock (PADCFGLOCK_GPP_J_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_J_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_D_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_R_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_J_0) GPI Interrupt Status (GPI_IS_GPP_D_0) GPI Interrupt Status (GPI_IS_GPP_R_0) GPI Interrupt Status (GPI_IS_GPP_J_0) GPI Interrupt Enable (GPI_IE_GPP_D_0) GPI Interrupt Enable (GPI_IE_GPP_R_0) GPI Interrupt Enable (GPI_IE_GPP_J_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_D_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_R_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_J_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_D_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_R_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_0) SMI Status (GPI_SMI_STS_GPP_D_0) SMI Enable (GPI_SMI_EN_GPP_D_0) NMI Status (GPI_NMI_STS_GPP_D_0) NMI Enable (GPI_NMI_EN_GPP_D_0) GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET) GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET) GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET) GPIO Hardware Information NMI Int Offset (NMI_INT_OFFSET) GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_D) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_R) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_J) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_13) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_13) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_14) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_14) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_15) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_15) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_16) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_16) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_17) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_17) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_18) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_18) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_19) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_19) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_20) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_20) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_21) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_21) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_22) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_22) Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_23) Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_23) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_R_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_R_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_13) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_13) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_14) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_14) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_15) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_15) Pad Configuration DW0 (PAD_CFG_DW0_GPP_J_16) Pad Configuration DW1 (PAD_CFG_DW1_GPP_J_16)
GPIO Commumity 1 Family Base Address (FAMBAR) Pad Base Address (PADBAR) Miscellaneous Configuration (MISCCFG) Pad Ownership (PAD_OWN_GPP_A_0) Pad Ownership (PAD_OWN_GPP_A_1) Pad Ownership (PAD_OWN_GPP_B_0) Pad Ownership (PAD_OWN_GPP_B_1) Pad Ownership (PAD_OWN_GPP_B_2) Pad Configuration Lock (PADCFGLOCK_GPP_A_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_A_0) Pad Configuration Lock (PADCFGLOCK_GPP_B_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_B_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_A_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_B_0) GPI Interrupt Status (GPI_IS_GPP_A_0) GPI Interrupt Status (GPI_IS_GPP_B_0) GPI Interrupt Enable (GPI_IE_GPP_A_0) GPI Interrupt Enable (GPI_IE_GPP_B_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_B_0) SMI Status (GPI_SMI_STS_GPP_B_0) SMI Enable (GPI_SMI_EN_GPP_B_0) NMI Status (GPI_NMI_STS_GPP_B_0) NMI Enable (GPI_NMI_EN_GPP_B_0) GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET) GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET) GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET) GPIO Hardware Information NMI Int Offset (NMI_INT_OFFSET) GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_A) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_B) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_13) Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_13) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_13) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_13) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_14) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_14) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_15) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_15) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_16) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_16) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_17) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_17) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_18) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_18) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_19) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_19) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_20) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_20) Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_21) Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_21)
GPIO Commumity 2 Family Base Address (FAMBAR) Pad Base Address (PADBAR) Miscellaneous Configuration (MISCCFG) Pad Ownership (PAD_OWN_DSW_0) Pad Ownership (PAD_OWN_DSW_1) Pad Configuration Lock (PADCFGLOCK_DSW_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_DSW_0) Host Software Pad Ownership (HOSTSW_OWN_DSW_0) GPI Interrupt Status (GPI_IS_DSW_0) GPI Interrupt Enable (GPI_IE_DSW_0) GPI General Purpose Events Status (GPI_GPE_STS_DSW_0) GPI General Purpose Events Enable (GPI_GPE_EN_DSW_0) GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET) GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET) GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET) GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET) GPIO Hardware Information Register Group (REGISTER_GROUP_DSW) Pad Configuration DW0 (PAD_CFG_DW0_GPD_0) Pad Configuration DW1 (PAD_CFG_DW1_GPD_0) Pad Configuration DW0 (PAD_CFG_DW0_GPD_1) Pad Configuration DW1 (PAD_CFG_DW1_GPD_1) Pad Configuration DW0 (PAD_CFG_DW0_GPD_2) Pad Configuration DW1 (PAD_CFG_DW1_GPD_2) Pad Configuration DW0 (PAD_CFG_DW0_GPD_3) Pad Configuration DW1 (PAD_CFG_DW1_GPD_3) Pad Configuration DW0 (PAD_CFG_DW0_GPD_4) Pad Configuration DW1 (PAD_CFG_DW1_GPD_4) Pad Configuration DW0 (PAD_CFG_DW0_GPD_5) Pad Configuration DW1 (PAD_CFG_DW1_GPD_5) Pad Configuration DW0 (PAD_CFG_DW0_GPD_6) Pad Configuration DW1 (PAD_CFG_DW1_GPD_6) Pad Configuration DW0 (PAD_CFG_DW0_GPD_7) Pad Configuration DW1 (PAD_CFG_DW1_GPD_7) Pad Configuration DW0 (PAD_CFG_DW0_GPD_8) Pad Configuration DW1 (PAD_CFG_DW1_GPD_8) Pad Configuration DW0 (PAD_CFG_DW0_GPD_9) Pad Configuration DW1 (PAD_CFG_DW1_GPD_9) Pad Configuration DW0 (PAD_CFG_DW0_GPD_10) Pad Configuration DW1 (PAD_CFG_DW1_GPD_10) Pad Configuration DW0 (PAD_CFG_DW0_GPD_11) Pad Configuration DW1 (PAD_CFG_DW1_GPD_11) Pad Configuration DW0 (PAD_CFG_DW0_GPD_12) Pad Configuration DW1 (PAD_CFG_DW1_GPD_12)
GPIO Commumity 3 Family Base Address (FAMBAR) Pad Base Address (PADBAR) Miscellaneous Configuration (MISCCFG) Pad Ownership (PAD_OWN_GPP_C_0) Pad Ownership (PAD_OWN_GPP_C_1) Pad Ownership (PAD_OWN_GPP_C_2) Pad Ownership (PAD_OWN_GPP_H_0) Pad Ownership (PAD_OWN_GPP_H_1) Pad Ownership (PAD_OWN_GPP_H_2) Pad Configuration Lock (PADCFGLOCK_GPP_C_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_C_0) Pad Configuration Lock (PADCFGLOCK_GPP_H_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_H_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_C_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_H_0) GPI Interrupt Status (GPI_IS_GPP_C_0) GPI Interrupt Status (GPI_IS_GPP_H_0) GPI Interrupt Enable (GPI_IE_GPP_C_0) GPI Interrupt Enable (GPI_IE_GPP_H_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_H_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_H_0) SMI Status (GPI_SMI_STS_GPP_C_0) SMI Enable (GPI_SMI_EN_GPP_C_0) NMI Status (GPI_NMI_STS_GPP_C_0) NMI Enable (GPI_NMI_EN_GPP_C_0) GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET) GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET) GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET) GPIO Hardware Information NMI Int Offset (NMI_INT_OFFSET) GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_C) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_H) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_13) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_13) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_14) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_14) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_15) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_15) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_16) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_16) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_17) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_17) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_18) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_18) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_19) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_19) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_20) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_20) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_21) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_21) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_22) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_22) Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_23) Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_23) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_13) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_13) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_14) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_14) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_15) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_15) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_16) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_16) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_17) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_17) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_18) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_18) Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_19) Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_19)
GPIO Commumity 4 Family Base Address (FAMBAR) Pad Base Address (PADBAR) Miscellaneous Configuration (MISCCFG) Pad Ownership (PAD_OWN_GPP_S_0) Pad Ownership (PAD_OWN_GPP_E_0) Pad Ownership (PAD_OWN_GPP_E_1) Pad Ownership (PAD_OWN_GPP_E_2) Pad Ownership (PAD_OWN_GPP_K_0) Pad Ownership (PAD_OWN_GPP_K_1) Pad Ownership (PAD_OWN_GPP_F_0) Pad Ownership (PAD_OWN_GPP_F_1) Pad Ownership (PAD_OWN_GPP_F_2) Pad Configuration Lock (PADCFGLOCK_GPP_S_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_S_0) Pad Configuration Lock (PADCFGLOCK_GPP_E_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_E_0) Pad Configuration Lock (PADCFGLOCK_GPP_K_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_K_0) Pad Configuration Lock (PADCFGLOCK_GPP_F_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_F_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_S_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_E_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_K_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_F_0) GPI Interrupt Status (GPI_IS_GPP_S_0) GPI Interrupt Status (GPI_IS_GPP_E_0) GPI Interrupt Status (GPI_IS_GPP_K_0) GPI Interrupt Status (GPI_IS_GPP_F_0) GPI Interrupt Enable (GPI_IE_GPP_S_0) GPI Interrupt Enable (GPI_IE_GPP_E_0) GPI Interrupt Enable (GPI_IE_GPP_K_0) GPI Interrupt Enable (GPI_IE_GPP_F_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_S_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_E_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_K_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_S_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_E_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_K_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_0) SMI Status (GPI_SMI_STS_GPP_E_0) SMI Enable (GPI_SMI_EN_GPP_E_0) NMI Status (GPI_NMI_STS_GPP_E_0) NMI Enable (GPI_NMI_EN_GPP_E_0) GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET) GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET) GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET) GPIO Hardware Information NMI Int Offset (NMI_INT_OFFSET) GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_S) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_E) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_K) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_F) PWM Control (PWMC) GPIO Serial Blink Enable (GP_SER_BLINK) GPIO Serial Blink Command/Status (GP_SER_CMDSTS) GPIO Serial Blink Data (GP_SER_DATA) GSX Controller Capabilities (GSX_CAP) GSX Channel-0 Capabilities DW0 (GSX_C0CAP_DW0) GSX Channel-0 Capabilities DW1 (GSX_C0CAP_DW1) GSX Channel-0 GP Input Level DW0 (GSX_C0GPILVL_DW0) GSX Channel-0 GP Input Level DW1 (GSX_C0GPILVL_DW1) GSX Channel-0 GP Output Level DW0 (GSX_C0GPOLVL_DW0) GSX Channel-0 GP Output Level DW1 (GSX_C0GPOLVL_DW1) GSX Channel-0 Command (GSX_C0CMD) GSX Channel-0 Test Mode (GSX_C0TM) Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_S_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_S_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_13) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_13) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_14) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_14) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_15) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_15) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_16) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_16) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_17) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_17) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_18) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_18) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_19) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_19) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_20) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_20) Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_21) Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_21) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_K_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_13) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_13) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_14) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_14) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_15) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_15) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_16) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_16) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_17) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_17) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_18) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_18) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_19) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_19) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_20) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_20) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_21) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_21) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_22) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_22) Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_23) Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_23)
GPIO Commumity 5 Family Base Address (FAMBAR) Pad Base Address (PADBAR) Miscellaneous Configuration (MISCCFG) Pad Ownership (PAD_OWN_GPP_I_0) Pad Ownership (PAD_OWN_GPP_I_1) Pad Ownership (PAD_OWN_GPP_I_2) Pad Configuration Lock (PADCFGLOCK_GPP_I_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_I_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_I_0) GPI Interrupt Status (GPI_IS_GPP_I_0) GPI Interrupt Enable (GPI_IE_GPP_I_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_I_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_I_0) SMI Status (GPI_SMI_STS_GPP_I_0) SMI Enable (GPI_SMI_EN_GPP_I_0) NMI Status (GPI_NMI_STS_GPP_I_0) NMI Enable (GPI_NMI_EN_GPP_I_0) GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET) GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET) GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET) GPIO Hardware Information NMI Int Offset (NMI_INT_OFFSET) GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET) GPIO Hardware Information Register Group (REGISTER_GROUP_GPP_I) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_0) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_0) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_1) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_1) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_2) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_2) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_3) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_3) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_4) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_4) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_5) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_5) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_6) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_6) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_7) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_7) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_8) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_8) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_9) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_9) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_10) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_10) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_11) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_11) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_12) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_12) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_13) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_13) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_14) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_14) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_15) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_15) Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_16) Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_16)
GSPI DMA DMA Transfer Source Address Low 0 (SAR_LO0) DMA Transfer Source Address High 0 (SAR_HI0) DMA Transfer Destination Address Low 0 (DAR_LO0) DMA Transfer Destination Address High 0 (DAR_HI0) Linked List Pointer Low 0 (LLP_LO0) Linked List Pointer High 0 (LLP_HI0) Control Register Low 0 (CTL_LO0) Control Register High 0 (CTL_HI0) Source Status 0 (SSTAT0) Destination Status 0 (DSTAT0) Source Status Address Low 0 (SSTATAR_LO0) Source Status Address High 0 (SSTATAR_HI0) Destination Status Address Low 0 (DSTATAR_LO0) Destination Status Address High 0 (DSTATAR_HI0) DMA Transfer Configuration Low 0 (CFG_LO0) DMA Transfer Configuration High 0 (CFG_HI0) Source Gather 0 (SGR0) Destination Scatter 0 (DSR0) DMA Transfer Source Address Low 1 (SAR_LO1) DMA Transfer Source Address High 1 (SAR_HI1) DMA Transfer Destination Address Low 1 (DAR_LO1) DMA Transfer Destination Address High 1 (DAR_HI1) Linked List Pointer Low 1 (LLP_LO1) Linked List Pointer High 1 (LLP_HI1) Control Register Low 1 (CTL_LO1) Control Register High 1 (CTL_HI1) Source Status 1 (SSTAT1) Destination Status 1 (DSTAT1) Source Status Address Low 1 (SSTATAR_LO1) Source Status Address High 1 (SSTATAR_HI1) Destination Status Address Low 1 (DSTATAR_LO1) Destination Status Address High 1 (DSTATAR_HI1) DMA Transfer Configuration Low 1 (CFG_LO1) DMA Transfer Configuration High 1 (CFG_HI1) Source Gather 1 (SGR1) Destination Scatter 1 (DSR1) Raw Interrupt Status (RawTfr) Raw Status for Block Interrupts (RawBlock) Raw Status for Source Transaction Interrupts (RawSrcTran) Raw Status for Destination Transaction Interrupts (RawDstTran) Raw Status for Error Interrupts (RawErr) Status for Transfer Interrupts (StatusTfr) Status for Block Interrupts (StatusBlock) Status for Source Transaction Interrupts (StatusSrcTran) Status for Destination Transaction Interrupts (StatusDstTran) Status for Error Interrupts (StatusErr) Mask for Transfer Interrupts (MaskTfr) Mask for Block Interrupts (MaskBlock) Mask for Source Transaction Interrupts (MaskSrcTran) Mask for Destination Transaction Interrupts (MaskDstTran) Mask for Error Interrupts (MaskErr) Clear for Transfer Interrupts (ClearTfr) Clear for Block Interrupts (ClearBlock) Clear for Source Transaction Interrupts (ClearSrcTran) Clear for Destination Transaction Interrupts (ClearDstTran) Clear for Error Interrupts (ClearErr) Combined Status (StatusInt) DMA Configuration (DmaCfgReg) DMA Channel Enable (ChEnReg) Global DMA Configuration (GLOBAL_CFG)
I2C DMA DMA Transfer Source Address Low 0 (SAR_LO0) DMA Transfer Source Address High 0 (SAR_HI0) DMA Transfer Destination Address Low 0 (DAR_LO0) DMA Transfer Destination Address High 0 (DAR_HI0) Linked List Pointer Low 0 (LLP_LO0) Linked List Pointer High 0 (LLP_HI0) Control Register Low 0 (CTL_LO0) Control Register High 0 (CTL_HI0) Source Status 0 (SSTAT0) Destination Status 0 (DSTAT0) Source Status Address Low 0 (SSTATAR_LO0) Source Status Address High 0 (SSTATAR_HI0) Destination Status Address Low 0 (DSTATAR_LO0) Destination Status Address High 0 (DSTATAR_HI0) DMA Transfer Configuration Low 0 (CFG_LO0) DMA Transfer Configuration High 0 (CFG_HI0) Source Gather 0 (SGR0) Destination Scatter 0 (DSR0) DMA Transfer Source Address Low 1 (SAR_LO1) DMA Transfer Source Address High 1 (SAR_HI1) DMA Transfer Destination Address Low 1 (DAR_LO1) DMA Transfer Destination Address High 1 (DAR_HI1) Linked List Pointer Low 1 (LLP_LO1) Linked List Pointer High 1 (LLP_HI1) Control Register Low 1 (CTL_LO1) Control Register High 1 (CTL_HI1) Source Status 1 (SSTAT1) Destination Status 1 (DSTAT1) Source Status Address Low 1 (SSTATAR_LO1) Source Status Address High 1 (SSTATAR_HI1) Destination Status Address Low 1 (DSTATAR_LO1) Destination Status Address High 1 (DSTATAR_HI1) DMA Transfer Configuration Low 1 (CFG_LO1) DMA Transfer Configuration High 1 (CFG_HI1) Source Gather 1 (SGR1) Destination Scatter 1 (DSR1) Raw Interrupt Status (RawTfr) Raw Status for Block Interrupts (RawBlock) Raw Status for Source Transaction Interrupts (RawSrcTran) Raw Status for Destination Transaction Interrupts (RawDstTran) Raw Status for Error Interrupts (RawErr) Status for Transfer Interrupts (StatusTfr) Status for Block Interrupts (StatusBlock) Status for Source Transaction Interrupts (StatusSrcTran) Status for Destination Transaction Interrupts (StatusDstTran) Status for Error Interrupts (StatusErr) Mask for Transfer Interrupts (MaskTfr) Mask for Block Interrupts (MaskBlock) Mask for Source Transaction Interrupts (MaskSrcTran) Mask for Destination Transaction Interrupts (MaskDstTran) Mask for Error Interrupts (MaskErr) Clear for Transfer Interrupts (ClearTfr) Clear for Block Interrupts (ClearBlock) Clear for Source Transaction Interrupts (ClearSrcTran) Clear for Destination Transaction Interrupts (ClearDstTran) Clear for Error Interrupts (ClearErr) Combined Status (StatusInt) DMA Configuration (DmaCfgReg) DMA Channel Enable (ChEnReg) Global DMA Configuration (GLOBAL_CFG)
I2C MMIO I2C Control (IC_CON) I2C Target Address (IC_TAR) I2C High Speed Master Mode Code Address (IC_HS_MADDR) Rx/Tx Data Buffer and Command (IC_DATA_CMD) Standard Speed I2C Clock SCL High Count (IC_SS_SCL_HCNT) Standard Speed I2C Clock SCL Low Count (IC_SS_SCL_LCNT) Fast Speed I2C Clock SCL High Count (IC_FS_SCL_HCNT) Fast Speed I2C Clock SCL Low Count (IC_FS_SCL_LCNT) High Speed I2C Clock SCL High Count (IC_HS_SCL_HCNT) High Speed I2C Clock SCL Low Count (IC_HS_SCL_LCNT) Interrupt Status (IC_INTR_STAT) Interrupt Mask (IC_INTR_MASK) Raw Interrupt Status (IC_RAW_INTR_STAT) Receive FIFO Threshold (IC_RX_TL) Transmit FIFO Threshold (IC_TX_TL) Clear Combined and Individual Interrupt (IC_CLR_INTR) Clear RX_UNDER Interrupt (IC_CLR_RX_UNDER) Clear RX_OVER Interrupt (IC_CLR_RX_OVER) Clear TX_OVER Interrupt (IC_CLR_TX_OVER) Clear RD_REQ Interrupt (IC_CLR_RD_REQ) Clear TX_ABRT Interrupt (IC_CLR_TX_ABRT) Clear RX_DONE Interrupt (IC_CLR_RX_DONE) Clear ACTIVITY Interrupt (IC_CLR_ACTIVITY) Clear STOP_DET Interrupt (IC_CLR_STOP_DET) Clear START_DET Interrupt (IC_CLR_START_DET) Clear GEN_CALL Interrupt (IC_CLR_GEN_CALL) I2C Enable (IC_ENABLE) I2C Status (IC_STATUS) Transmit FIFO Level (IC_TXFLR) Receive FIFO Level (IC_RXFLR) SDA Hold Time Length (IC_SDA_HOLD) Transmit Abort Source (IC_TX_ABRT_SOURCE) DMA Control (IC_DMA_CR) DMA Transmit Data Level (IC_DMA_TDLR) Receive Data Level (IC_DMA_RDLR) SDA Setup (IC_SDA_SETUP) ACK General Call (IC_ACK_GENERAL_CALL) I2C Enable Status (IC_ENABLE_STATUS) SS and FS Spike Suppression Limit (IC_FS_SPKLEN) HS Spike Suppression Limit (IC_HS_SPKLEN)
I3C DMA REG CR_SETUP_0 (CR_SETUP_0) REG IBI_SETUP_0 (IBI_SETUP_0) REG CHUNK_CONTROL_0 (CHUNK_CONTROL_0) REG RH_INTR_STATUS_0 (RH_INTR_STATUS_0) REG RH_INTR_STATUS_ENABLE_0 (RH_INTR_STATUS_ENABLE_0) REG RH_INTR_SIGNAL_ENABLE_0 (RH_INTR_SIGNAL_ENABLE_0) REG RH_INTR_FORCE_0 (RH_INTR_FORCE_0) REG RH_STATUS_0 (RH_STATUS_0) REG RH_CONTROL_0 (RH_CONTROL_0) REG RH_OPERATION1_0 (RH_OPERATION1_0) REG RH_OPERATION2_0 (RH_OPERATION2_0) REG RH_CMD_RING_BASE_LO_0 (RH_CMD_RING_BASE_LO_0) REG RH_CMD_RING_BASE_HI_0 (RH_CMD_RING_BASE_HI_0) REG RH_RESP_RING_BASE_LO_0 (RH_RESP_RING_BASE_LO_0) REG RH_RESP_RING_BASE_HI_0 (RH_RESP_RING_BASE_HI_0) REG RH_IBI_STATUS_RING_BASE_LO_0 (RH_IBI_STATUS_RING_BASE_LO_0) REG RH_IBI_STATUS_RING_BASE_HI_0 (RH_IBI_STATUS_RING_BASE_HI_0) REG RH_IBI_DATA_RING_BASE_LO_0 (RH_IBI_DATA_RING_BASE_LO_0) REG RH_IBI_DATA_RING_BASE_HI_0 (RH_IBI_DATA_RING_BASE_HI_0) REG RHS_CONTROL_0 (RHS_CONTROL_0) REG RH0_OFFSET_0 (RH0_OFFSET_0) REG RH1_OFFSET_0 (RH1_OFFSET_0) REG RH2_OFFSET_0 (RH2_OFFSET_0) REG RH3_OFFSET_0 (RH3_OFFSET_0) REG RH4_OFFSET_0 (RH4_OFFSET_0) REG RH5_OFFSET_0 (RH5_OFFSET_0) REG RH6_OFFSET_0 (RH6_OFFSET_0) REG RH7_OFFSET_0 (RH7_OFFSET_0) REG CR_SETUP_2 (CR_SETUP_2) REG IBI_SETUP_2 (IBI_SETUP_2) REG CHUNK_CONTROL_2 (CHUNK_CONTROL_2) REG RH_INTR_STATUS_2 (RH_INTR_STATUS_2) REG RH_INTR_STATUS_ENABLE_2 (RH_INTR_STATUS_ENABLE_2) REG RH_INTR_SIGNAL_ENABLE_2 (RH_INTR_SIGNAL_ENABLE_2) REG RH_INTR_FORCE_2 (RH_INTR_FORCE_2) REG RH_STATUS_2 (RH_STATUS_2) REG RH_CONTROL_2 (RH_CONTROL_2) REG RH_OPERATION1_2 (RH_OPERATION1_2) REG RH_OPERATION2_2 (RH_OPERATION2_2) REG RH_CMD_RING_BASE_LO_2 (RH_CMD_RING_BASE_LO_2) REG RH_CMD_RING_BASE_HI_2 (RH_CMD_RING_BASE_HI_2) REG RH_RESP_RING_BASE_LO_2 (RH_RESP_RING_BASE_LO_2) REG RH_RESP_RING_BASE_HI_2 (RH_RESP_RING_BASE_HI_2) REG RH_IBI_STATUS_RING_BASE_LO_2 (RH_IBI_STATUS_RING_BASE_LO_2) REG RH_IBI_STATUS_RING_BASE_HI_2 (RH_IBI_STATUS_RING_BASE_HI_2) REG RH_IBI_DATA_RING_BASE_LO_2 (RH_IBI_DATA_RING_BASE_LO_2) REG RH_IBI_DATA_RING_BASE_HI_2 (RH_IBI_DATA_RING_BASE_HI_2) REG RHS_CONTROL_1 (RHS_CONTROL_1) REG RH0_OFFSET_1 (RH0_OFFSET_1) REG RH1_OFFSET_1 (RH1_OFFSET_1) REG RH2_OFFSET_1 (RH2_OFFSET_1) REG RH3_OFFSET_1 (RH3_OFFSET_1) REG RH4_OFFSET_1 (RH4_OFFSET_1) REG RH5_OFFSET_1 (RH5_OFFSET_1) REG RH6_OFFSET_1 (RH6_OFFSET_1) REG RH7_OFFSET_1 (RH7_OFFSET_1) REG CR_SETUP_1 (CR_SETUP_1) REG IBI_SETUP_1 (IBI_SETUP_1) REG CHUNK_CONTROL_1 (CHUNK_CONTROL_1) REG RH_INTR_STATUS_1 (RH_INTR_STATUS_1) REG RH_INTR_STATUS_ENABLE_1 (RH_INTR_STATUS_ENABLE_1) REG RH_INTR_SIGNAL_ENABLE_1 (RH_INTR_SIGNAL_ENABLE_1) REG RH_INTR_FORCE_1 (RH_INTR_FORCE_1) REG RH_STATUS_1 (RH_STATUS_1) REG RH_CONTROL_1 (RH_CONTROL_1) REG RH_OPERATION1_1 (RH_OPERATION1_1) REG RH_OPERATION2_1 (RH_OPERATION2_1) REG RH_CMD_RING_BASE_LO_1 (RH_CMD_RING_BASE_LO_1) REG RH_CMD_RING_BASE_HI_1 (RH_CMD_RING_BASE_HI_1) REG RH_RESP_RING_BASE_LO_1 (RH_RESP_RING_BASE_LO_1) REG RH_RESP_RING_BASE_HI_1 (RH_RESP_RING_BASE_HI_1) REG RH_IBI_STATUS_RING_BASE_LO_1 (RH_IBI_STATUS_RING_BASE_LO_1) REG RH_IBI_STATUS_RING_BASE_HI_1 (RH_IBI_STATUS_RING_BASE_HI_1) REG RH_IBI_DATA_RING_BASE_LO_1 (RH_IBI_DATA_RING_BASE_LO_1) REG RH_IBI_DATA_RING_BASE_HI_1 (RH_IBI_DATA_RING_BASE_HI_1) REG CR_SETUP_3 (CR_SETUP_3) REG IBI_SETUP_3 (IBI_SETUP_3) REG CHUNK_CONTROL_3 (CHUNK_CONTROL_3) REG RH_INTR_STATUS_3 (RH_INTR_STATUS_3) REG RH_INTR_STATUS_ENABLE_3 (RH_INTR_STATUS_ENABLE_3) REG RH_INTR_SIGNAL_ENABLE_3 (RH_INTR_SIGNAL_ENABLE_3) REG RH_INTR_FORCE_3 (RH_INTR_FORCE_3) REG RH_STATUS_3 (RH_STATUS_3) REG RH_CONTROL_3 (RH_CONTROL_3) REG RH_OPERATION1_3 (RH_OPERATION1_3) REG RH_OPERATION2_3 (RH_OPERATION2_3) REG RH_CMD_RING_BASE_LO_3 (RH_CMD_RING_BASE_LO_3) REG RH_CMD_RING_BASE_HI_3 (RH_CMD_RING_BASE_HI_3) REG RH_RESP_RING_BASE_LO_3 (RH_RESP_RING_BASE_LO_3) REG RH_RESP_RING_BASE_HI_3 (RH_RESP_RING_BASE_HI_3) REG RH_IBI_STATUS_RING_BASE_LO_3 (RH_IBI_STATUS_RING_BASE_LO_3) REG RH_IBI_STATUS_RING_BASE_HI_3 (RH_IBI_STATUS_RING_BASE_HI_3) REG RH_IBI_DATA_RING_BASE_LO_3 (RH_IBI_DATA_RING_BASE_LO_3) REG RH_IBI_DATA_RING_BASE_HI_3 (RH_IBI_DATA_RING_BASE_HI_3)
I3C MMIO REG HCI_VERSION (HCI_VERSION) REG DEVICE_CONTROL (DEVICE_CONTROL) REG DEVICE_ADDR (DEVICE_ADDR) REG DEVICE_CAPABILITIES (DEVICE_CAPABILITIES) REG RESET_CTRL (RESET_CTRL) REG PRESENT_STATE (PRESENT_STATE) REG INTR_STATUS (INTR_STATUS) REG INTR_STATUS_ENABLE (INTR_STATUS_ENABLE) REG INTR_SIGNAL_ENABLE (INTR_SIGNAL_ENABLE) REG INTR_FORCE (INTR_FORCE) REG DAT_SECTION_OFFSET (DAT_SECTION_OFFSET) REG DCT_SECTION_OFFSET (DCT_SECTION_OFFSET) REG RING_HEADERS_SECTION_OFFSET (RING_HEADERS_SECTION_OFFSET) REG PIO_SECTION_OFFSET (PIO_SECTION_OFFSET) REG EXTCAPS_SECTION_OFFSET (EXTCAPS_SECTION_OFFSET) REG IBI_NOTIFY_CTRL (IBI_NOTIFY_CTRL) REG DEV_ADDR_TABLE1_LOC1 (DEV_ADDR_TABLE1_LOC1) REG DEV_ADDR_TABLE1_LOC2 (DEV_ADDR_TABLE1_LOC2) REG DEV_ADDR_TABLE2_LOC1 (DEV_ADDR_TABLE2_LOC1) REG DEV_ADDR_TABLE2_LOC2 (DEV_ADDR_TABLE2_LOC2) REG DEV_ADDR_TABLE3_LOC1 (DEV_ADDR_TABLE3_LOC1) REG DEV_ADDR_TABLE3_LOC2 (DEV_ADDR_TABLE3_LOC2) REG DEV_ADDR_TABLE4_LOC1 (DEV_ADDR_TABLE4_LOC1) REG DEV_ADDR_TABLE4_LOC2 (DEV_ADDR_TABLE4_LOC2) REG DEV_ADDR_TABLE5_LOC1 (DEV_ADDR_TABLE5_LOC1) REG DEV_ADDR_TABLE5_LOC2 (DEV_ADDR_TABLE5_LOC2) REG DEV_ADDR_TABLE6_LOC1 (DEV_ADDR_TABLE6_LOC1) REG DEV_ADDR_TABLE6_LOC2 (DEV_ADDR_TABLE6_LOC2) REG DEV_ADDR_TABLE7_LOC1 (DEV_ADDR_TABLE7_LOC1) REG DEV_ADDR_TABLE7_LOC2 (DEV_ADDR_TABLE7_LOC2) REG DEV_ADDR_TABLE8_LOC1 (DEV_ADDR_TABLE8_LOC1) REG DEV_ADDR_TABLE8_LOC2 (DEV_ADDR_TABLE8_LOC2) REG COMMAND_QUEUE_PORT (COMMAND_QUEUE_PORT) REG RESPONSE_QUEUE_PORT (RESPONSE_QUEUE_PORT) REG DATA_PORT (DATA_PORT) REG IBI_PORT (IBI_PORT) REG QUEUE_THLD_CTRL (QUEUE_THLD_CTRL) REG DATA_BUFFER_THLD_CTRL (DATA_BUFFER_THLD_CTRL) REG QUEUE_SIZE_CTRL (QUEUE_SIZE_CTRL) REG DEV_CHAR_TABLE1_LOC1 (DEV_CHAR_TABLE1_LOC1) REG DEV_CHAR_TABLE1_LOC2 (DEV_CHAR_TABLE1_LOC2) REG DEV_CHAR_TABLE1_LOC3 (DEV_CHAR_TABLE1_LOC3) REG DEV_CHAR_TABLE1_LOC4 (DEV_CHAR_TABLE1_LOC4) REG DEV_CHAR_TABLE2_LOC1 (DEV_CHAR_TABLE2_LOC1) REG DEV_CHAR_TABLE2_LOC2 (DEV_CHAR_TABLE2_LOC2) REG DEV_CHAR_TABLE2_LOC3 (DEV_CHAR_TABLE2_LOC3) REG DEV_CHAR_TABLE2_LOC4 (DEV_CHAR_TABLE2_LOC4) REG DEV_CHAR_TABLE3_LOC1 (DEV_CHAR_TABLE3_LOC1) REG DEV_CHAR_TABLE3_LOC2 (DEV_CHAR_TABLE3_LOC2) REG DEV_CHAR_TABLE3_LOC3 (DEV_CHAR_TABLE3_LOC3) REG DEV_CHAR_TABLE3_LOC4 (DEV_CHAR_TABLE3_LOC4) REG DEV_CHAR_TABLE4_LOC1 (DEV_CHAR_TABLE4_LOC1) REG DEV_CHAR_TABLE4_LOC2 (DEV_CHAR_TABLE4_LOC2) REG DEV_CHAR_TABLE4_LOC3 (DEV_CHAR_TABLE4_LOC3) REG DEV_CHAR_TABLE4_LOC4 (DEV_CHAR_TABLE4_LOC4) REG DEV_CHAR_TABLE5_LOC1 (DEV_CHAR_TABLE5_LOC1) REG DEV_CHAR_TABLE5_LOC2 (DEV_CHAR_TABLE5_LOC2) REG DEV_CHAR_TABLE5_LOC3 (DEV_CHAR_TABLE5_LOC3) REG DEV_CHAR_TABLE5_LOC4 (DEV_CHAR_TABLE5_LOC4) REG DEV_CHAR_TABLE6_LOC1 (DEV_CHAR_TABLE6_LOC1) REG DEV_CHAR_TABLE6_LOC2 (DEV_CHAR_TABLE6_LOC2) REG DEV_CHAR_TABLE6_LOC3 (DEV_CHAR_TABLE6_LOC3) REG DEV_CHAR_TABLE6_LOC4 (DEV_CHAR_TABLE6_LOC4) REG DEV_CHAR_TABLE7_LOC1 (DEV_CHAR_TABLE7_LOC1) REG DEV_CHAR_TABLE7_LOC2 (DEV_CHAR_TABLE7_LOC2) REG DEV_CHAR_TABLE7_LOC3 (DEV_CHAR_TABLE7_LOC3) REG DEV_CHAR_TABLE7_LOC4 (DEV_CHAR_TABLE7_LOC4) REG DEV_CHAR_TABLE8_LOC1 (DEV_CHAR_TABLE8_LOC1) REG DEV_CHAR_TABLE8_LOC2 (DEV_CHAR_TABLE8_LOC2) REG DEV_CHAR_TABLE8_LOC3 (DEV_CHAR_TABLE8_LOC3) REG DEV_CHAR_TABLE8_LOC4 (DEV_CHAR_TABLE8_LOC4) REG HW_IDENTIFICATION_HEADER (HW_IDENTIFICATION_HEADER) REG COMP_MANUFACTURER (COMP_MANUFACTURER) REG COMP_VERSION (COMP_VERSION) REG COMP_TYPE (COMP_TYPE) REG BUS_TIMING_HEADER (BUS_TIMING_HEADER) REG SCL_I3C_OD_TIMING (SCL_I3C_OD_TIMING) REG SCL_I3C_PP_TIMING (SCL_I3C_PP_TIMING) REG SCL_I2C_FM_TIMING (SCL_I2C_FM_TIMING) REG SCL_I2C_FMP_TIMING (SCL_I2C_FMP_TIMING) REG SCL_I2C_SS_TIMING (SCL_I2C_SS_TIMING) REG SCL_EXT_LCNT_TIMING (SCL_EXT_LCNT_TIMING) REG SCL_EXT_TERMN_LCNT_TIMING (SCL_EXT_TERMN_LCNT_TIMING) REG SDA_HOLD_SWITCH_DLY_TIMING (SDA_HOLD_SWITCH_DLY_TIMING) REG BUS_FREE_TIMING (BUS_FREE_TIMING) REG DS_EXTCAP_HEADER (DS_EXTCAP_HEADER) REG QUEUE_STATUS_LEVEL (QUEUE_STATUS_LEVEL) REG DATA_BUFFER_STATUS_LEVEL (DATA_BUFFER_STATUS_LEVEL) REG PRESENT_STATE_DEBUG (PRESENT_STATE_DEBUG) REG MASTER_EXT_HEADER (MASTER_EXT_HEADER) REG MASTER_CONFIG (MASTER_CONFIG)
Integrated Sensor Hub (ISH) PCI Configuration Device Id And Vendor Id Register (DEVVENDID) Status And Command (STATUSCOMMAND) Revision Id And Class Code (REVCLASSCODE) Cache Line Latency Header And Bist (CLLATHEADERBIST) Base Address Register (BAR) Base Address Register High (BAR_HIGH) Base Address Register1 (BAR1) Base Address Register1 High (BAR1_HIGH) Subsystem Vendor And Subsystem Id (SUBSYSTEMID) Expansion Rom Base Address (EXPANSION_ROM_BASEADDR) Capabilities Pointer (CAPABILITYPTR) Interrupt Register (INTERRUPTREG) Pcie Capabilities Register (PCIECAPREG) Power Management Capability Id (POWERCAPID) Power Management Control And Status Register (PMECTRLSTATUS) Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD) Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG) Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG) Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG) D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG) General Purpose Read Write Register1 (GEN_PCI_REGRW1) General Purpose Read Write Register2 (GEN_PCI_REGRW2) General Purpose Read Write Register3 (GEN_PCI_REGRW3) General Purpose Read Write Register4 (GEN_PCI_REGRW4) General Purpose Input Register (GEN_INPUT_REG) Msix Capability Register (MSIX_CAP_REG) Msix Table Pointer (MSIX_TABLE_PTR) Msix Pba Pointer (MSIX_PBA_PTR) Msi Capability Register (MSI_CAP_REG) Msi Message Low Address (MSI_ADDR_LOW) Msi Message High Address (MSI_ADDR_HIGH) Msi Message Data (MSI_MSG_DATA) Msi Mask Register (MSI_MASK) Msi Pending Register (MSI_PENDING) Ltr Capability Header Register (LTR_CAP_HEAD) Ltr Max Snoop Non Snoop Latency Register (MAX_LATENCY_REGISTER)
Intel(R) Management Engine Interface (MEI) PCI Configuration HECI ID (HECI1_ID) HECI Command (HECI1_CMD) HECI Status (HECI1_STS) Revision ID And Class Code (HECI1_RID_CC) Cache Line Size (HECI1_CLS) Master Latency Timer (HECI1_MLT) Header Type (HECI1_HTYPE) Built In Self-Test (HECI1_BIST) HECI MMIO Base Address Low (HECI1_MMIO_MBAR_LO) HECI MMIO Base Address High (HECI1_MMIO_MBAR_HI) Sub System Identifiers (HECI1_SS) Capabilities Pointer (HECI1_CAP) Interrupt Information (HECI1_INTR) Minimum Grant (HECI1_MGNT) Maximum Latency (HECI1_MLAT) Host Firmware Status (HECI1_HFS) Miscellaneous Shadow (HECI1_MISC_SHDW) General Status Shadow 1 (HECI1_GS_SHDW1) Host General Status (HECI1_H_GS1) PCI Power Management Capability ID (HECI1_PID) PCI Power Management Capabilities (HECI1_PC) PCI Power Management Control And Status (HECI1_PMCS) General Status Shadow 2 (HECI1_GS_SHDW2) General Status Shadow 3 (HECI1_GS_SHDW3) General Status Shadow 4 (HECI1_GS_SHDW4) General Status Shadow 5 (HECI1_GS_SHDW5) Host General Status 2 (HECI1_H_GS2) Host General Status 3 (HECI1_H_GS3) Message Signaled Interrupt Identifiers (HECI1_MID) Message Signaled Interrupt Message Control (HECI1_MC) Message Signaled Interrupt Message Address (HECI1_MA) Message Signaled Interrupt Upper Address (HECI1_MUA) Message Signaled Interrupt Message Data (HECI1_MD) HECI Interrupt Delivery Mode (HECI1_HIDM) Vendor Specific Capability Register (HECI1_VSCR) Vendor Specific Extended Capability Register (HECI1_VSEC) SW LTR Pointer Register (HECI1_SWLTRPTR) Device Idle Pointer Register (HECI1_DEVIDLEPTR) Device Idle Power On Latency (HECI1_DEVIDLEPOL) DevIdle Power Control Enabled Register (HECI1_PWRCTRLEN) Host Extend Register Status (HECI1_HERS) Host Extend Register DW1 (HECI1_HER1) Host Extend Register DW2 (HECI1_HER2) Host Extend Register DW3 (HECI1_HER3) Host Extend Register DW4 (HECI1_HER4) Host Extend Register DW5 (HECI1_HER5) Host Extend Register DW6 (HECI1_HER6) Host Extend Register DW7 (HECI1_HER7) Host Extend Register DW8 (HECI1_HER8)
Intel® High Definition Audio MMIO Global Capabilities (GCAP) Minor Version (VMIN) Major Version (VMAJ) Output Payload Capability (OUTPAY) Input Payload Capability (INPAY) Global Control (GCTL) Wake Enable (WAKEEN) Wake Status (WAKESTS) Global Status (GSTS) Global Capabilities 2 (GCAP2) Linked List Capabilities Header (LLCH) Output Stream Payload Capability (OUTSTRMPAY) Input Stream Payload Capability (INSTRMPAY) Interrupt Control (INTCTL) Interrupt Status (INTSTS) Wall Clock Counter (WALCLK) Stream Synchronization (SSYNC) CORB Lower Base Address (CORBLBASE) CORB Upper Base Address (CORBUBASE) CORB Write Pointer (CORBWP) CORB Read Pointer (CORBRP) CORB Control (CORBCTL) CORB Status (CORBSTS) CORB Size (CORBSIZE) Immediate Command (IC) Immediate Response (IR) Immediate Command Status (ICS) DMA Position Lower Base Address (DPLBASE) DMA Position Upper Base Address (DPUBASE) Input Stream Descriptor x Control (ISD0CTL_B0) Input Stream Descriptor x Control (ISD0CTL_B2) Input Stream Descriptor x Status (ISD0STS) Input Stream Descriptor x Link Position in Buffer (ISD0LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD0CBL) Input Stream Descriptor x Last Valid Index (ISD0LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD0FIFOW) Input Stream Descriptor x FIFO Size (ISD0FIFOS) Input Stream Descriptor x Format (ISD0FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD0BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD0BDLPUBA) Input Stream Descriptor x Control (ISD1CTL_B0) Input Stream Descriptor x Control (ISD1CTL_B2) Input Stream Descriptor x Status (ISD1STS) Input Stream Descriptor x Link Position in Buffer (ISD1LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD1CBL) Input Stream Descriptor x Last Valid Index (ISD1LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD1FIFOW) Input Stream Descriptor x FIFO Size (ISD1FIFOS) Input Stream Descriptor x Format (ISD1FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD1BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD1BDLPUBA) Input Stream Descriptor x Control (ISD2CTL_B0) Input Stream Descriptor x Control (ISD2CTL_B2) Input Stream Descriptor x Status (ISD2STS) Input Stream Descriptor x Link Position in Buffer (ISD2LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD2CBL) Input Stream Descriptor x Last Valid Index (ISD2LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD2FIFOW) Input Stream Descriptor x FIFO Size (ISD2FIFOS) Input Stream Descriptor x Format (ISD2FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD2BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD2BDLPUBA) Input Stream Descriptor x Control (ISD3CTL_B0) Input Stream Descriptor x Control (ISD3CTL_B2) Input Stream Descriptor x Status (ISD3STS) Input Stream Descriptor x Link Position in Buffer (ISD3LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD3CBL) Input Stream Descriptor x Last Valid Index (ISD3LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD3FIFOW) Input Stream Descriptor x FIFO Size (ISD3FIFOS) Input Stream Descriptor x Format (ISD3FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD3BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD3BDLPUBA) Input Stream Descriptor x Control (ISD4CTL_B0) Input Stream Descriptor x Control (ISD4CTL_B2) Input Stream Descriptor x Status (ISD4STS) Input Stream Descriptor x Link Position in Buffer (ISD4LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD4CBL) Input Stream Descriptor x Last Valid Index (ISD4LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD4FIFOW) Input Stream Descriptor x FIFO Size (ISD4FIFOS) Input Stream Descriptor x Format (ISD4FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD4BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD4BDLPUBA) Input Stream Descriptor x Control (ISD5CTL_B0) Input Stream Descriptor x Control (ISD5CTL_B2) Input Stream Descriptor x Status (ISD5STS) Input Stream Descriptor x Cyclic Buffer Length (ISD5CBL) Input Stream Descriptor x Last Valid Index (ISD5LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD5FIFOW) Input Stream Descriptor x FIFO Size (ISD5FIFOS) Input Stream Descriptor x Format (ISD5FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD5BDLPUBA) Input Stream Descriptor x Control (ISD6CTL_B0) Input Stream Descriptor x Control (ISD6CTL_B2) Input Stream Descriptor x Status (ISD6STS) Input Stream Descriptor x Link Position in Buffer (ISD6LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD6CBL) Input Stream Descriptor x Last Valid Index (ISD6LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD6FIFOW) Input Stream Descriptor x FIFO Size (ISD6FIFOS) Input Stream Descriptor x Format (ISD6FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD6BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD6BDLPUBA) Input Stream Descriptor x Control (ISD7CTL_B0) Input Stream Descriptor x Control (ISD7CTL_B2) Input Stream Descriptor x Status (ISD7STS) Input Stream Descriptor x Link Position in Buffer (ISD7LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD7CBL) Input Stream Descriptor x Last Valid Index (ISD7LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD7FIFOW) Input Stream Descriptor x FIFO Size (ISD7FIFOS) Input Stream Descriptor x Format (ISD7FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD7BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD7BDLPUBA) Input Stream Descriptor x Control (ISD8CTL_B0) Input Stream Descriptor x Control (ISD8CTL_B2) Input Stream Descriptor x Status (ISD8STS) Input Stream Descriptor x Link Position in Buffer (ISD8LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD8CBL) Input Stream Descriptor x Last Valid Index (ISD8LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD8FIFOW) Input Stream Descriptor x FIFO Size (ISD8FIFOS) Input Stream Descriptor x Format (ISD8FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD8BDLPUBA) Input Stream Descriptor x Control (ISD9CTL_B0) Input Stream Descriptor x Control (ISD9CTL_B2) Input Stream Descriptor x Status (ISD9STS) Input Stream Descriptor x Cyclic Buffer Length (ISD9CBL) Input Stream Descriptor x Last Valid Index (ISD9LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD9FIFOW) Input Stream Descriptor x FIFO Size (ISD9FIFOS) Input Stream Descriptor x Format (ISD9FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD9BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD9BDLPUBA) Output Stream Descriptor x Control (OSD0CTL_B0) Output Stream Descriptor x Control (OSD0CTL_B2) Output Stream Descriptor x Status (OSD0STS) Output Stream Descriptor x Link Position in Buffer (OSD0LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD0CBL) Output Stream Descriptor x Last Valid Index (OSD0LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD0FIFOW) Output Stream Descriptor x FIFO Size (OSD0FIFOS) Output Stream Descriptor x Format (OSD0FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD0BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD0BDLPUBA) Output Stream Descriptor x Control (OSD1CTL_B0) Output Stream Descriptor x Control (OSD1CTL_B2) Output Stream Descriptor x Status (OSD1STS) Output Stream Descriptor x Link Position in Buffer (OSD1LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD1CBL) Output Stream Descriptor x Last Valid Index (OSD1LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD1FIFOW) Output Stream Descriptor x FIFO Size (OSD1FIFOS) Output Stream Descriptor x Format (OSD1FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD1BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD1BDLPUBA) Output Stream Descriptor x Control (OSD2CTL_B0) Output Stream Descriptor x Control (OSD2CTL_B2) Output Stream Descriptor x Status (OSD2STS) Output Stream Descriptor x Link Position in Buffer (OSD2LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD2CBL) Output Stream Descriptor x Last Valid Index (OSD2LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD2FIFOW) Output Stream Descriptor x FIFO Size (OSD2FIFOS) Output Stream Descriptor x Format (OSD2FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD2BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD2BDLPUBA) Output Stream Descriptor x Control (OSD3CTL_B0) Output Stream Descriptor x Control (OSD3CTL_B2) Output Stream Descriptor x Status (OSD3STS) Output Stream Descriptor x Link Position in Buffer (OSD3LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD3CBL) Output Stream Descriptor x Last Valid Index (OSD3LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD3FIFOW) Output Stream Descriptor x FIFO Size (OSD3FIFOS) Output Stream Descriptor x Format (OSD3FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD3BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD3BDLPUBA) Output Stream Descriptor x Control (OSD4CTL_B0) Output Stream Descriptor x Control (OSD4CTL_B2) Output Stream Descriptor x Status (OSD4STS) Output Stream Descriptor x Link Position in Buffer (OSD4LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD4CBL) Output Stream Descriptor x Last Valid Index (OSD4LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD4FIFOW) Output Stream Descriptor x FIFO Size (OSD4FIFOS) Output Stream Descriptor x Format (OSD4FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD4BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD4BDLPUBA) Output Stream Descriptor x Control (OSD5CTL_B0) Output Stream Descriptor x Control (OSD5CTL_B2) Output Stream Descriptor x Status (OSD5STS) Output Stream Descriptor x Link Position in Buffer (OSD5LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD5CBL) Output Stream Descriptor x Last Valid Index (OSD5LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD5FIFOW) Output Stream Descriptor x FIFO Size (OSD5FIFOS) Output Stream Descriptor x Format (OSD5FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD5BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD5BDLPUBA) Output Stream Descriptor x Control (OSD6CTL_B0) Output Stream Descriptor x Control (OSD6CTL_B2) Output Stream Descriptor x Status (OSD6STS) Output Stream Descriptor x Link Position in Buffer (OSD6LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD6CBL) Output Stream Descriptor x Last Valid Index (OSD6LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD6FIFOW) Output Stream Descriptor x FIFO Size (OSD6FIFOS) Output Stream Descriptor x Format (OSD6FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD6BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD6BDLPUBA) Output Stream Descriptor x Control (OSD7CTL_B0) Output Stream Descriptor x Control (OSD7CTL_B2) Output Stream Descriptor x Status (OSD7STS) Output Stream Descriptor x Link Position in Buffer (OSD7LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD7CBL) Output Stream Descriptor x Last Valid Index (OSD7LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD7FIFOW) Output Stream Descriptor x FIFO Size (OSD7FIFOS) Output Stream Descriptor x Format (OSD7FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD7BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD7BDLPUBA) Output Stream Descriptor x Control (OSD8CTL_B0) Output Stream Descriptor x Control (OSD8CTL_B2) Output Stream Descriptor x Status (OSD8STS) Output Stream Descriptor x Link Position in Buffer (OSD8LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD8CBL) Output Stream Descriptor x Last Valid Index (OSD8LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD8FIFOW) Output Stream Descriptor x FIFO Size (OSD8FIFOS) Output Stream Descriptor x Format (OSD8FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD8BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD8BDLPUBA) DMA Resume Capability Header (DRSMCH) DMA Resume Control (DRSMCTL) Input Stream Descriptor x DMA Position in Buffer Resume (ISD0DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD1DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD2DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD3DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD4DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD5DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD6DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD7DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD8DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD9DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (OSD0DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (OSD1DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (OSD2DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (OSD3DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (OSD4DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (OSD5DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (OSD6DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (OSD7DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (OSD8DPIBR) Software Position Based FIFO Capability Header (SPBFCH) Software Position Based FIFO Control (SPBFCTL) Input / Output Stream Descriptor x Software Position in Buffer (ISD0SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD0MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (ISD1SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD1MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (ISD2SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD2MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (ISD3SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD3MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (ISD4SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD4MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (ISD5SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD5MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (ISD6SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD6MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (ISD7SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD7MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (ISD8SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD8MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (ISD9SPIB) Input / Output Stream Descriptor x Max FIFO Size (ISD9MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (OSD0SPIB) Input / Output Stream Descriptor x Max FIFO Size (OSD0MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (OSD1SPIB) Input / Output Stream Descriptor x Max FIFO Size (OSD1MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (OSD2SPIB) Input / Output Stream Descriptor x Max FIFO Size (OSD2MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (OSD3SPIB) Input / Output Stream Descriptor x Max FIFO Size (OSD3MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (OSD4SPIB) Input / Output Stream Descriptor x Max FIFO Size (OSD4MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (OSD5SPIB) Input / Output Stream Descriptor x Max FIFO Size (OSD5MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (OSD6SPIB) Input / Output Stream Descriptor x Max FIFO Size (OSD6MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (OSD7SPIB) Input / Output Stream Descriptor x Max FIFO Size (OSD7MAXFIFOS) Input / Output Stream Descriptor x Software Position in Buffer (OSD8SPIB) Input / Output Stream Descriptor x Max FIFO Size (OSD8MAXFIFOS) Processing Pipe Capability Header (PPCH) Processing Pipe Control (PPCTL) Processing Pipe Status (PPSTS) Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC0LLPL) Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC0LLPU) Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC0LDPL) Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC0LDPU) Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC1LLPL) Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC1LLPU) Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC1LDPL) Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC1LDPU) Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC2LLPL) Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC2LLPU) Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC2LDPL) Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC2LDPU) Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC3LLPL) Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC3LLPU) Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC3LDPL) Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC3LDPU) Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC4LLPL) Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC4LLPU) Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC4LDPL) Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC4LDPU) Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC5LLPL) Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC5LLPU) Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC5LDPL) Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC5LDPU) Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC6LLPL) Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC6LLPU) Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC6LDPL) Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC6LDPU) Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC7LLPL) Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC7LLPU) Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC7LDPL) Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC7LDPU) Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC8LLPL) Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC8LLPU) Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC8LDPL) Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC8LDPU) Input / Output Processing Pipes Link Connection on Control (OPPLC0CTL) Input / Output Processing Pipes Link Connection on Format (OPPLC0FMT) Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC0LLPL) Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC0LLPU) Input / Output Processing Pipes Link Connection on Control (OPPLC1CTL) Input / Output Processing Pipes Link Connection on Format (OPPLC1FMT) Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC1LLPL) Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC1LLPU) Input / Output Processing Pipes Link Connection on Control (OPPLC2CTL) Input / Output Processing Pipes Link Connection on Format (OPPLC2FMT) Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC2LLPL) Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC2LLPU) Input / Output Processing Pipes Link Connection on Control (OPPLC3CTL) Input / Output Processing Pipes Link Connection on Format (OPPLC3FMT) Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC3LLPL) Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC3LLPU) Input / Output Processing Pipes Link Connection on Control (OPPLC4CTL) Input / Output Processing Pipes Link Connection on Format (OPPLC4FMT) Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC4LLPL) Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC4LLPU) Input / Output Processing Pipes Link Connection on Control (OPPLC5CTL) Input / Output Processing Pipes Link Connection on Format (OPPLC5FMT) Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC5LLPL) Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC5LLPU) Input / Output Processing Pipes Link Connection on Control (OPPLC6CTL) Input / Output Processing Pipes Link Connection on Format (OPPLC6FMT) Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC6LLPL) Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC6LLPU) Input / Output Processing Pipes Link Connection on Control (OPPLC7CTL) Input / Output Processing Pipes Link Connection on Format (OPPLC7FMT) Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC7LLPL) Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC7LLPU) Input / Output Processing Pipes Link Connection on Control (OPPLC8CTL) Input / Output Processing Pipes Link Connection on Format (OPPLC8FMT) Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC8LLPL) Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC8LLPU) Multiple Links Capability Header (MLCH) Multiple Links Capability Declaration (MLCD) Link x Capabilities (LCAP0) Link x Control (LCTL0) Link x SDI IDentifiers (LSDIID0) Link x Per Stream Output Overhead (LPSOO0) Link x Per Stream Input Overhead (LPSIO0) Link x Wall Frame Counter (LWALFC0) Link x 6 MHz Output Payload Capability (LOUTPAY60) Link x 12 MHz Output Payload Capability (LOUTPAY120) Link x 24 MHz Output Payload Capability (LOUTPAY240) Link x 48 MHz Output Payload Capability (LOUTPAY480) Link x 96 MHz Output Payload Capability (LOUTPAY960) Link x 192 MHz Output Payload Capability (LOUTPAY1920) Link x 6 MHz Input Payload Capability (LINPAY60) Link x 12 MHz Input Payload Capability (LINPAY120) Link x 24 MHz Input Payload Capability (LINPAY240) Link x 48 MHz Input Payload Capability (LINPAY480) Link x 96 MHz Input Payload Capability (LINPAY960) Link x 192 MHz Input Payload Capability (LINPAY1920) Link x Capabilities (LCAP1) Link x Control (LCTL1) Link x SDI IDentifiers (LSDIID1) Link x Per Stream Output Overhead (LPSOO1) Link x Per Stream Input Overhead (LPSIO1) Link x Wall Frame Counter (LWALFC1) Link x 6 MHz Output Payload Capability (LOUTPAY61) Link x 12 MHz Output Payload Capability (LOUTPAY121) Link x 24 MHz Output Payload Capability (LOUTPAY241) Link x 48 MHz Output Payload Capability (LOUTPAY481) Link x 96 MHz Output Payload Capability (LOUTPAY961) Link x 192 MHz Output Payload Capability (LOUTPAY1921) Link x 6 MHz Input Payload Capability (LINPAY61) Link x 12 MHz Input Payload Capability (LINPAY121) Link x 24 MHz Input Payload Capability (LINPAY241) Link x 48 MHz Input Payload Capability (LINPAY481) Link x 96 MHz Input Payload Capability (LINPAY961) Link x 192 MHz Input Payload Capability (LINPAY1921) Input / Output Stream Descriptor x DMA Position in Buffer (ISD0DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (ISD1DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (ISD2DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (ISD3DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (ISD4DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (ISD5DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (ISD6DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (ISD7DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (ISD8DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (ISD9DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (OSD0DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (OSD1DPIB) Input / Output Stream Descriptor x DMA Position in Buffer (OSD3DPIB) Latency Tolerance Reporting Policy (LTRP) Input Stream Repeat Count (INRC) D0i3 Control (D0I3C) Power Transition Delay Control (PTDC) Function Configuration (FNCFG) Wall Clock Counter Alias (WALCLKA) Input/Output Stream Descriptor x Link Position in Buffer (ISD0LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (ISD1LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (ISD2LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (ISD3LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (ISD4LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (ISD5LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (ISD6LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (ISD7LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (ISD8LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (ISD9LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (OSD0LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (OSD1LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (OSD2LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (OSD3LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (OSD4LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (OSD5LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (OSD6LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (OSD7LPIBA) Input/Output Stream Descriptor x Link Position in Buffer (OSD8LPIBA)
PCIe* PCI Configuration Identifiers (ID) Device Command (CMD) Primary Status (PSTS) Revision ID (RID_CC) Cache Line Size (CLS) Header Type (HTYPE) Base Address Register 0 (BAR0) Base Address Register 1 (BAR1) Bus Numbers (BNUM_SLT) I/O Base And Limit (IOBL) Secondary Status (SSTS) Memory Base And Limit (MBL) Prefetchable Memory Base And Limit (PMBL) Prefetchable Memory Base Upper 32 Bits (PMBU32) Prefetchable Memory Limit Upper 32 Bits (PMLU32) Capabilities List Pointer (CAPP) Interrupt Information Byte 0 (INTRB0) Interrupt Information Byte 1 (INTRB1) Bridge Control (BCTRL) Capabilities List (CLIST) PCI Express Capabilities (XCAP) Device Capabilities (DCAP) Device Control (DCTL) Device Status (DSTS) Link Capabilities (LCAP) Link Control (LCTL) Link Status (LSTS) Slot Capabilities (SLCAP) Slot Control (SLCTL) Slot Status (SLSTS) Root Control (RCTL) Root Capabilities (ROOTCAP) Root Status (RSTS) Device Capabilities 2 (DCAP2) Device Control 2 (DCTL2) Link Capabilities 2 (LCAP2) Link Control 2 (LCTL2) Link Status 2 (LSTS2) Message Signaled Interrupt Identifiers (MID) Message Signaled Interrupt Message (MC) Message Signaled Interrupt Message Address (MA) Message Signaled Interrupt Message Upper Address (MUA) Message Signaled Interrupt Message Data (MD) Subsystem Vendor Capability (SVCAP) Subsystem Vendor IDs (SVID) Power Management Capability (PMCAP) PCI Power Management Capabilities (PMC) PCI Power Management Control (PMCS) Advanced Error Extended (AECH) Uncorrectable Error Status (UES) Uncorrectable Error Mask (UEM) Uncorrectable Error Severity (UEV) Correctable Error Status (CES) Correctable Error Mask (CEM) Advanced Error Capabilities And Control (AECC) Root Error Command (REC) Root Error Status (RES) Error Source Identification (ESID) PTM Extended Capability Header (PTMECH) PTM Capability Register (PTMCAPR) PTM Control Register (PTMCTLR) L1 Sub-States Extended Capability Header (L1SECH) L1 Sub-States Capabilities (L1SCAP) L1 Sub-States Control 1 (L1SCTL1) L1 Sub-States Control 2 (L1SCTL2) ACS Extended Capability Header (ACSECH) ACS Capability Register (ACSCAPR) ACS Control Register (ACSCTLR) Port VC Capability Register 1 (PVCCR1) Port VC Capability 2 (PVCC2) Port VC Control (PVCC) Port VC Status (PVCS) Virtual Channel 0 Resource Capability (V0VCRC) Virtual Channel 0 Resource Control (V0CTL) Virtual Channel 0 Resource Status (V0STS) Virtual Channel 1 Resource Capability (V1VCRC) Virtual Channel 1 Resource Control (V1CTL) Virtual Channel 1 Resource Status (V1STS) DPC Extended Capability Header (DPCECH) DPC Capability Register (DPCCAPR) DPC Control Register (DPCCTLR) DPC Status Register (DPCSR) DPC Error Source ID Register (DPCESIDR) RP PIO Status Register (RPPIOSR) RP PIO Mask Register (RPPIOMR) RP PIO Severity Register (RPPIOVR) RP PIO SysError Register (RPPIOSER) RP PIO Exception Register (RPPIOER) RP PIO Header Log DW1 Register (RPPIOHLR_DW1) RP PIO Header Log DW2 Register (RPPIOHLR_DW2) RP PIO Header Log DW3 Register (RPPIOHLR_DW3) RP PIO Header Log DW4 Register (RPPIOHLR_DW4) Secondary PCI Express Extended Capability Header (SPEECH) Link Control 3 (LCTL3) Lane Error Status (LES) Lane 0 And Lane 1 Equalization Control (L01EC) Lane 2 And Lane 3 Equalization Control (L23EC) Lane 4 And Lane 5 Equalization Control (L45EC) Lane 6 And Lane 7 Equalization Control (L67EC) Lane 8 And Lane 9 Equalization Control (L89EC) Lane 10 And Lane 11 Equalization Control (L1011EC) Lane 12 And Lane 13 Equalization Control (L1213EC) Lane 14 And Lane 15 Equalization Control (L1415EC) Data Link Feature Extended Capability Header (DLFECH) Data Link Feature Capabilities Register (DLFCAP) Data Link Feature Status Register (DLFSTS) Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH) Physical Layer 16.0 GT/s Status Register (PL16S) Physical Layer 16.0 GT/s Local Data Parity Mismatch Status Register (PL16LDPMS) Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS) Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS) Physical Layer 16.0 GT/s Lane 01 Equalization Control Register (PL16L01EC) Physical Layer 16.0 GT/s Lane 23 Equalization Control Register (PL16L23EC) Physical Layer 16.0 GT/s Lane 45 Equalization Control Register (PL16L45EC) Physical Layer 16.0 GT/s Lane 67 Equalization Control Register (PL16L67EC) Physical Layer 16.0 GT/s Lane 89 Equalization Control Register (PL16L89EC) Physical Layer 16.0 GT/s Lane 1011 Equalization Control Register (PL16L1011EC) Physical Layer 16.0 GT/s Lane 1213 Equalization Control Register (PL16L1213EC) Physical Layer 16.0 GT/s Lane 1415 Equalization Control Register (PL16L1415EC) Physical Layer 32.0 GT/s Extended Capability Header (G5ECH) Physical Layer 32.0 GT/s Capability Register (G5CAP) Physical Layer 32.0 GT/s Control Register (G5CTL) Physical Layer 32.0 GT/s Status Register (G5STS) Receiver Modified TS Data 1 Register (RCVDMODTSDATA1) Receiver Modified TS Data 2 Register (RCVDMODTSDATA2) Transmitted Modified TS Data 1 Register (TRNSMODTSDATA1) Transmitted Modified TS Data 2 Register (TRNSMODTSDATA2) Alternate Protocol Extended Capability Header (APEC) Alternate Protocol Capabilities Register (APCAPR) Alternate Protocol Control Register (APCTRLR) Alternate Protocol Data 1 Register (APD1R) Alternate Protocol Data 2 Register (APD2R) Alternate Protocol Selective Enable Mask Register (APSEMR) Multicast Extended Capability Header (MCECH) Multicast Extended Capability Register (MCAPR) Multicast Control Register (MCCTLR) Multicast Base Address Register 1 (MCBADRR1) Multicast Base Address Register 2 (MCBADRR2) Multicast Receive Register (MCRR) Multicast Block All Register (MCBAR) Multicast Block Untranslated Register (MCBUR) Multicast Overlay BAR 1 (MCOB1) Multicast Overlay BAR 2 (MCOB2) VNN Removal Control (VNNREMCTL) VNN Removal Save And Restore Hardware Contexts 1 (VNNRSNRC1) Physical Layer 16.0 GT/s Margining Extended Capability Header (PL16MECH) Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status Byte 0 & 1 (PL16MPCPSB01) Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status Byte 2 & 3 (PL16MPCPSB23) Physical Layer 16.0 GT/s Lane0 Margin Control and Status Register (PL16L0MCS) Physical Layer 16.0 GT/s Lane1 Margin Control and Status Register (PL16L1MCS) Physical Layer 16.0 GT/s Lane2 Margin Control and Status Register (PL16L2MCS) Physical Layer 16.0 GT/s Lane3 Margin Control and Status Register (PL16L3MCS) Physical Layer 16.0 GT/s Lane4 Margin Control and Status Register (PL16L4MCS) Physical Layer 16.0 GT/s Lane5 Margin Control and Status Register (PL16L5MCS) Physical Layer 16.0 GT/s Lane6 Margin Control and Status Register (PL16L6MCS) Physical Layer 16.0 GT/s Lane7 Margin Control and Status Register (PL16L7MCS) Physical Layer 16.0 GT/s Lane8 Margin Control and Status Register (PL16L8MCS) Physical Layer 16.0 GT/s Lane9 Margin Control and Status Register (PL16L9MCS) Physical Layer 16.0 GT/s Lane10 Margin Control and Status Register (PL16L10MCS) Physical Layer 16.0 GT/s Lane11 Margin Control and Status Register (PL16L11MCS) Physical Layer 16.0 GT/s Lane12 Margin Control and Status Register (PL16L12MCS) Physical Layer 16.0 GT/s Lane13 Margin Control and Status Register (PL16L13MCS) Physical Layer 16.0 GT/s Lane14 Margin Control and Status Register (PL16L14MCS) Physical Layer 16.0 GT/s Lane15 Margin Control and Status Register (PL16L15MCS)
PMC MMIO General PM Configuration A (GEN_PMCON_A) General PM Configuration B (GEN_PMCON_B) Configured Revision ID (CRID) Extended Test Mode Register 3 (ETR3) SET STRAP MSG LOCK (SSML) SET STRAP MSG CONTROL (SSMC) SET STRAP MSG DATA (SSMD) Configured Revision ID (CRID_UIP) SLP S0 DEBUG REG0 (SLP_S0_DBG_0) SLP S0 DEBUG REG1 (SLP_S0_DBG_1) SLP S0 DEBUG REG2 (SLP_S0_DBG_2) HSIO Power Management Configuration Reg 1 (MODPHY_PM_CFG1) HSIO Power Management Configuration Reg 2 (MODPHY_PM_CFG2) HSIO Power Management Configuration Reg 3 (MODPHY_PM_CFG3) HSIO Power Management Configuration Reg 4 (MODPHY_PM_CFG4) HSIO Power Management Configuration Reg 5 (MODPHY_PM_CFG5) HSIO Power Management Configuration Reg 6 (MODPHY_PM_CFG6) EXT FET RAMP CFG (EXT_FET_RAMP_CFG) VCCIN AUX CONFIG Register (VCCIN_AUX_CFG) Always Running Timer Value 31:0 (ARTV_31_0) Always Running Timer Value 31:0 (ARTV_63_32) Always Running Timer Value Control (ARTV_CTRL) Timed GPIO Control 0 (TGPIOCTL0) Timed GPIO 0 Comparator Value 31:0 (TGPIOCOMPV0_31_0) Timed GPIO Comparator Value 63:32 (TGPIOCOMPV0_63_32) Timed GPIO0 Periodic Interval Value 31_0 (TGPIOPIV0_31_0) Timed GPIO 0 Periodic Interval Value 63_32 (TGPIOPIV0_63_32) Timed GPIO Time Capture Register 31_0 (TGPIOTCV0_31_0) Timed GPIO0 Time Capture Register 63_32 (TGPIOTCV0_63_32) Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV0_31_0) Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV0_63_32) Timed GPIO0 Event Counter Register 31_0 (TGPIOEC0_31_0) Timed GPIO0 Event Counter Register 63_32 (TGPIOEC0_63_32) Timed GPIO Control 1 (TGPIOCTL1) Timed GPIO 1 Comparator Value 31:0 (TGPIOCOMPV1_31_0) Timed GPIO Comparator Value 63:32 (TGPIOCOMPV1_63_32) Timed GPIO1 Periodic Interval Value 31_0 (TGPIOPIV1_31_0) Timed GPIO 1 Periodic Interval Value 63_32 (TGPIOPIV1_63_32) Timed GPIO Time Capture Register 31_0 (TGPIOTCV1_31_0) Timed GPIO Time Capture Register 63_32 (TGPIOTCV1_63_32) Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV1_31_0) Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV1_63_32) Timed GPIO1 Event Counter Register 31_0 (TGPIOEC1_31_0) Timed GPIO Event Counter Register 63_32 (TGPIOEC1_63_32) Min Temperature (MIN_TEMP) Max Temperature (MAX_TEMP) Catastrophic Trip Point Enable (CTEN) EC Thermal Sensor Reporting Enable (ECRPTEN) Throttle Level (TL) SW Throttle (SWTHROT) Throttle Levels Enable (TLEN) Thermal Sensor Alert High Value (TSAHV) Thermal Sensor Alert Low Value (TSALV) Thermal Alert Trip Status (TAS) PCH Hot Level Control (PHLC) Temperature Sensor Control and Status (TSS0) SoC-to-IOE Force Thermal Throttling Control (S2I_FTT_CTRL) Wake Alarm Device Timer: AC (WADT_AC) Wake Alarm Device Timer: DC (WADT_DC) Wake Alarm Device Expired Timer: AC (WADT_EXP_AC) Wake Alarm Device Expired Timer: DC (WADT_EXP_DC) Power and Reset Status (PRSTS) Power Management Configuration Reg 1 (PM_CFG) S3 Power Gating Policies (S3_PWRGATE_POL) S4 Power Gating Policies (S4_PWRGATE_POL) S5 Power Gating Policies (S5_PWRGATE_POL) DeepSx Configuration (DSX_CFG) Power Management Configuration Reg 2 (PM_CFG2) Power Management Configuration Reg 3 (PM_CFG3) Power Management Configuration Reg 4 (PM_CFG4) CPU Early Power-on Configuration (CPU_EPOC) ADR Enable (ADR_EN) ACPI Timer Control (ACPI_TMR_CTL) ADR General Configuration (ADR_GEN_CFG) Last TSC Alarm Value[31:0] (TSC_ALARM_LO) Last TSC Alarm Value[63:32] (TSC_ALARM_HI) GPIO Configuration (GPIO_CFG) Host Partition Reset Causes (HPR_CAUSE0) Latency Limit Residency 0 (LAT_LIM_RES_0) Latency Limit Residency 1 (LAT_LIM_RES_1) Latency Limit Residency 2 (LAT_LIM_RES_2) SLP_S0 Residency (SLP_S0_RESIDENCY) Latency Limit Control (LATENCY_LIMIT_CONTROL) ADR Control and Status (ADR_CTRL_STS) ACPI Control (ACTL) S0 Residency (S0_RES) PGD PG_ACK Status Register 0 (PPASR0) PGD PG_ACK Status Register 1 (PPASR1) PGD PFET Enable Ack Status Register 0 (PPFEAR0) PGD PFET Enable Ack Status Register 1 (PPFEAR1) PGD PG_REQ Status Register 0 (PPRSR0) PGD PG_REQ Status Register 1 (PPRSR1) ST_PG_FDIS_PMC - Register 1 (ST_PG_FDIS_PMC_1) ST_PG_FDIS_PMC - Register 2 (ST_PG_FDIS_PMC_2)
SATA MXTBA MSI-X Table Entries 0 Message Lower Address (MXTE0MLA) MSI-X Table Entries 0 Message Upper Address (MXTE0MUA) MSI-X Table Entries 0 Message Data (MXTE0MD) MSI-X Table Entries 0 Vector Control (MXTE0VC) MSI-X Table Entries 1 Message Lower Address (MXTE1MLA) MSI-X Table Entries 1 Message Upper Address (MXTE1MUA) MSI-X Table Entries 1 Message Data (MXTE1MD) MSI-X Table Entries 1 Vector Control (MXTE1VC) MSI-X Table Entries 2 Message Lower Address (MXTE2MLA) MSI-X Table Entries 2 Message Upper Address (MXTE2MUA) MSI-X Table Entries 2 Message Data (MXTE2MD) MSI-X Table Entries 2 Vector Control (MXTE2VC) MSI-X Table Entries 3 Message Lower Address (MXTE3MLA) MSI-X Table Entries 3 Message Upper Address (MXTE3MUA) MSI-X Table Entries 3 Message Data (MXTE3MD) MSI-X Table Entries 3 Vector Control (MXTE3VC) MSI-X Table Entries 4 Message Lower Address (MXTE4MLA) MSI-X Table Entries 4 Message Upper Address (MXTE4MUA) MSI-X Table Entries 4 Message Data (MXTE4MD) MSI-X Table Entries 4 Vector Control (MXTE4VC) MSI-X Table Entries 5 Message Lower Address (MXTE5MLA) MSI-X Table Entries 5 Message Upper Address (MXTE5MUA) MSI-X Table Entries 5 Message Data (MXTE5MD) MSI-X Table Entries 5 Vector Control (MXTE5VC) MSI-X Table Entries 6 Message Lower Address (MXTE6MLA) MSI-X Table Entries 6 Message Upper Address (MXTE6MUA) MSI-X Table Entries 6 Message Data (MXTE6MD) MSI-X Table Entries 6 Vector Control (MXTE6VC) MSI-X Table Entries 7 Message Lower Address (MXTE7MLA) MSI-X Table Entries 7 Message Upper Address (MXTE7MUA) MSI-X Table Entries 7 Message Data (MXTE7MD) MSI-X Table Entries 7 Vector Control (MXTE7VC)
SPI MMIO BIOS Flash Primary Region (BIOS_BFPREG) Hardware Sequencing Flash Status and Control (BIOS_HSFSTS_CTL) Flash Address (BIOS_FADDR) Discrete Lock Bits (BIOS_DLOCK) Flash Data (BIOS_FDATA0) Flash Data (BIOS_FDATA1) Flash Data (BIOS_FDATA2) Flash Data (BIOS_FDATA3) Flash Data (BIOS_FDATA4) Flash Data (BIOS_FDATA5) Flash Data (BIOS_FDATA6) Flash Data (BIOS_FDATA7) Flash Data (BIOS_FDATA8) Flash Data (BIOS_FDATA9) Flash Data (BIOS_FDATA10) Flash Data (BIOS_FDATA11) Flash Data (BIOS_FDATA12) Flash Data (BIOS_FDATA13) Flash Data (BIOS_FDATA14) Flash Data (BIOS_FDATA15) Flash Region Access Permissions (BIOS_FRACC) Flash Region (BIOS_FREG0) Flash Region (BIOS_FREG1) Flash Region (BIOS_FREG2) Flash Region (BIOS_FREG3) Flash Region (BIOS_FREG4) Flash Region (BIOS_FREG5) Flash Region (BIOS_FREG6) Flash Region (BIOS_FREG7) Flash Region (BIOS_FREG8) Flash Region (BIOS_FREG9) Flash Region (BIOS_FREG10) Flash Region (BIOS_FREG11) Flash Protected Range (BIOS_FPR0) Flash Protected Range (BIOS_FPR1) Flash Protected Range (BIOS_FPR2) Flash Protected Range (BIOS_FPR3) Flash Protected Range (BIOS_FPR4) Global Protected Range 0 (BIOS_GPR0) Secondary Flash Region Access Permissions (BIOS_SFRACC) Flash Descriptor Observability Control (BIOS_FDOC) Flash Descriptor Observability Data (BIOS_FDOD) Additional Flash Control (BIOS_AFC) Vendor Specific Component Capabilities for Component 0 (BIOS_SFDP0_VSCC0) Vendor Specific Component Capabilities for Component 1 (BIOS_SFDP1_VSCC1) Parameter Table Index (BIOS_PTINX) Parameter Table Data (BIOS_PTDATA) SPI Bus Requester Status (BIOS_SBRS) Flash Region (BIOS_FREG12) Flash Region (BIOS_FREG13) Flash Region (BIOS_FREG14) Flash Region (BIOS_FREG15)
THC MMIO Port Touch Host Controller Control Register (THC_M_PRT_CONTROL) THC SPI Bus Configuration Register (THC_M_PRT_SPI_CFG) THC SPI Bus Read Opcode Register (THC_M_PRT_SPI_ICRRD_OPCODE) THC SPI Bus Read Opcode Register (THC_M_PRT_SPI_DMARD_OPCODE) THC SPI Bus Write Opcode Register (THC_M_PRT_SPI_WR_OPCODE) THC Interrupt Enable Register (THC_M_PRT_INT_EN) THC Interrupt Status Register (THC_M_PRT_INT_STATUS) THC Error Cause Register (THC_M_PRT_ERR_CAUSE) THC SW sequencing Control (THC_M_PRT_SW_SEQ_CNTRL) THC SW sequencing Status (THC_M_PRT_SW_SEQ_STS) THC SW Sequencing Data DW0 or SPI Address Register (THC_M_PRT_SW_SEQ_DATA0_ADDR) THC SW sequencing Data DW1 (THC_M_PRT_SW_SEQ_DATA1) THC SW sequencing Data DW2 (THC_M_PRT_SW_SEQ_DATA2) THC SW sequencing Data DW3 (THC_M_PRT_SW_SEQ_DATA3) THC SW sequencing Data DW4 (THC_M_PRT_SW_SEQ_DATA4) THC SW sequencing Data DW5 (THC_M_PRT_SW_SEQ_DATA5) THC SW sequencing Data DW6 (THC_M_PRT_SW_SEQ_DATA6) THC SW sequencing Data DW7 (THC_M_PRT_SW_SEQ_DATA7) THC SW sequencing Data DW8 (THC_M_PRT_SW_SEQ_DATA8) THC SW sequencing Data DW9 (THC_M_PRT_SW_SEQ_DATA9) THC SW sequencing Data DW10 (THC_M_PRT_SW_SEQ_DATA10) THC SW sequencing Data DW11 (THC_M_PRT_SW_SEQ_DATA11) THC SW sequencing Data DW12 (THC_M_PRT_SW_SEQ_DATA12) THC SW sequencing Data DW13 (THC_M_PRT_SW_SEQ_DATA13) THC SW sequencing Data DW14 (THC_M_PRT_SW_SEQ_DATA14) THC SW sequencing Data DW15 (THC_M_PRT_SW_SEQ_DATA15) THC SW sequencing Data DW16 (THC_M_PRT_SW_SEQ_DATA16) THC Write PRD Base Address Register Low (THC_M_PRT_WPRD_BA_LOW) THC Write PRD Base Address Register High (THC_M_PRT_WPRD_BA_HI) THC Write DMA Control (THC_M_PRT_WRITE_DMA_CNTRL) THC Write Interrupt Status (THC_M_PRT_WRITE_INT_STS) THC device address for the bulk write (THC_M_PRT_WR_BULK_ADDR) THC Device Interrupt Cause Register Address (THC_M_PRT_DEV_INT_CAUSE_ADDR) THC Device Interrupt Cause Register Value (THC_M_PRT_DEV_INT_CAUSE_REG_VAL) THC TXDMA Frame Count (THC_M_PRT_TX_FRM_CNT) THC TXDMA Packet Count (THC_M_PRT_TXDMA_PKT_CNT) THC Device Interrupt Count on this port (THC_M_PRT_DEVINT_CNT) Touch Device Interrupt Cause register Format Configuration Register 1 (THC_M_PRT_DEVINT_CFG_1) Touch Device Interrupt Cause register Format Configuration Register 2 (THC_M_PRT_DEVINT_CFG_2) THC Read PRD Base Address Low for the 1st RXDMA (THC_M_PRT_RPRD_BA_LOW_1) THC Read PRD Base Address High for the 1st RXDMA (THC_M_PRT_RPRD_BA_HI_1) THC Read PRD Control for the 1st RXDMA (THC_M_PRT_RPRD_CNTRL_1) THC Read DMA Control for the 1st RXDMA (THC_M_PRT_READ_DMA_CNTRL_1) THC Read Interrupt Status for the 1st RXDMA (THC_M_PRT_READ_DMA_INT_STS_1) THC Read DMA Error Register for the 1st RXDMA (THC_M_PRT_READ_DMA_ERR_1) Touch Sequencer GuC Tail Offset Address Low for the 1st RXDMA (THC_M_PRT_GUC_OFFSET_LOW_1) Touch Sequencer GuC Tail Offset Address High for the 1st RXDMA (THC_M_PRT_GUC_OFFSET_HI_1) Touch Host Controller GuC Work Queue Item Size for the 1st RXDMA (THC_M_PRT_GUC_WORKQ_ITEM_SZ_1) Touch Host Controller GuC Control register for the 1st RXDMA (THC_M_PRT_GUC_WORKQ_SZ_1) Touch Sequencer Control for the 1st DMA (THC_M_PRT_TSEQ_CNTRL_1) Touch Sequencer GuC Doorbell Address Low for the 1st RXDMA (THC_M_PRT_GUC_DB_ADDR_LOW_1) Touch Sequencer GuC Doorbell Address High for the 1st RXDMA (THC_M_PRT_GUC_DB_ADDR_HI_1) Touch Sequencer GuC Doorbell Data (THC_M_PRT_GUC_DB_DATA_1) Touch Sequencer GuC Tail Offset Initial Value for the 1st RXDMA (THC_M_PRT_GUC_OFFSET_INITVAL_1) THC Device Address for the bulk/touch data read for the 2nd RXDMA (THC_M_PRT_RD_BULK_ADDR_1) THC Gfx/SW Doorbell Count from the 1st Stream RXDMA on this port (THC_M_PRT_DB_CNT_1) THC Frame Count from the 1st Stream RXDMA on this port (THC_M_PRT_FRM_CNT_1) THC Micro Frame Count from the 1st Stream RXDMA on this port (THC_M_PRT_UFRM_CNT_1) THC Packet Count from the 1st Stream RXDMA on this port (THC_M_PRT_RXDMA_PKT_CNT_1) THC Software Interrupt Count from the 1st Stream RXDMA on this port (THC_M_PRT_SWINT_CNT_1) Touch Sequencer Frame Drop Counter for the 1st RXDMA (THC_M_PRT_FRAME_DROP_CNT_1) THC Coaescing 1 (THC_M_PRT_COALESCE_1) THC Read PRD Base Address Low for the 2nd RXDMA (THC_M_PRT_RPRD_BA_LOW_2) THC Read PRD Base Address High for the 2nd RXDMA (THC_M_PRT_RPRD_BA_HI_2) THC Read PRD Control for the 2nd RXDMA (THC_M_PRT_RPRD_CNTRL_2) THC Read DMA Control for the 2nd RXDMA (THC_M_PRT_READ_DMA_CNTRL_2) THC Read Interrupt Status for the 2nd RXDMA (THC_M_PRT_READ_DMA_INT_STS_2) THC Read DMA Error Register for the 2nd RXDMA (THC_M_PRT_READ_DMA_ERR_2) Touch Sequencer GuC Tail Offset Address Low for the 2nd RXDMA (THC_M_PRT_GUC_OFFSET_LOW_2) Touch Sequencer GuC Tail Offset Address High for the 2nd RXDMA (THC_M_PRT_GUC_OFFSET_HI_2) Touch Host Controller GuC Work Queue Item Size for the 2nd RXDMA (THC_M_PRT_GUC_WORKQ_ITEM_SZ_2) Touch Host Controller GuC Control register for the 2nd RXDMA (THC_M_PRT_GUC_WORKQ_SZ_2) Touch Sequencer Control for the 2nd DMA (THC_M_PRT_TSEQ_CNTRL_2) Touch Sequencer GuC Doorbell Address Low for the 2nd RXDMA (THC_M_PRT_GUC_DB_ADDR_LOW_2) Touch Sequencer GuC Doorbell Address High for the 2nd RXDMA (THC_M_PRT_GUC_DB_ADDR_HI_2) Touch Sequencer GuC Doorbell Data for PRD2 (THC_M_PRT_GUC_DB_DATA_2) Touch Sequencer GuC Tail Offset Initial Value for the 2nd RXDMA (THC_M_PRT_GUC_OFFSET_INITVAL_2) THC Device Address for the bulk/touch data read for the 1st RXDMA (THC_M_PRT_RD_BULK_ADDR_2) THC Gfx/SW Doorbell Count from the 2nd Stream RXDMA on this port (THC_M_PRT_DB_CNT_2) THC Frame Count from the 2nd Stream RXDMA on this port (THC_M_PRT_FRM_CNT_2) THC Micro Frame Count from the 2nd Stream RXDMA on this port (THC_M_PRT_UFRM_CNT_2) THC Packet Count from the 2nd Stream RXDMA on this port (THC_M_PRT_RXDMA_PKT_CNT_2) THC Software Interrupt Count from the 2nd Stream RXDMA on this port (THC_M_PRT_SWINT_CNT_2) Touch Sequencer Frame Drop Counter for the 2nd RXDMA (THC_M_PRT_FRAME_DROP_CNT_2) THC Coaescing 2 (THC_M_PRT_COALESCE_2)
UART DMA DMA Transfer Source Address Low 0 (SAR_LO0) DMA Transfer Source Address High 0 (SAR_HI0) DMA Transfer Destination Address Low 0 (DAR_LO0) DMA Transfer Destination Address High 0 (DAR_HI0) Linked List Pointer Low 0 (LLP_LO0) Linked List Pointer High 0 (LLP_HI0) Control Register Low 0 (CTL_LO0) Control Register High 0 (CTL_HI0) Source Status 0 (SSTAT0) Destination Status 0 (DSTAT0) Source Status Address Low 0 (SSTATAR_LO0) Source Status Address High 0 (SSTATAR_HI0) Destination Status Address Low 0 (DSTATAR_LO0) Destination Status Address High 0 (DSTATAR_HI0) DMA Transfer Configuration Low 0 (CFG_LO0) DMA Transfer Configuration High 0 (CFG_HI0) Source Gather 0 (SGR0) Destination Scatter 0 (DSR0) DMA Transfer Source Address Low 1 (SAR_LO1) DMA Transfer Source Address High 1 (SAR_HI1) DMA Transfer Destination Address Low 1 (DAR_LO1) DMA Transfer Destination Address High 1 (DAR_HI1) Linked List Pointer Low 1 (LLP_LO1) Linked List Pointer High 1 (LLP_HI1) Control Register Low 1 (CTL_LO1) Control Register High 1 (CTL_HI1) Source Status 1 (SSTAT1) Destination Status 1 (DSTAT1) Source Status Address Low 1 (SSTATAR_LO1) Source Status Address High 1 (SSTATAR_HI1) Destination Status Address Low 1 (DSTATAR_LO1) Destination Status Address High 1 (DSTATAR_HI1) DMA Transfer Configuration Low 1 (CFG_LO1) DMA Transfer Configuration High 1 (CFG_HI1) Source Gather 1 (SGR1) Destination Scatter 1 (DSR1) Raw Interrupt Status (RawTfr) Raw Status for Block Interrupts (RawBlock) Raw Status for Source Transaction Interrupts (RawSrcTran) Raw Status for Destination Transaction Interrupts (RawDstTran) Raw Status for Error Interrupts (RawErr) Status for Transfer Interrupts (StatusTfr) Status for Block Interrupts (StatusBlock) Status for Source Transaction Interrupts (StatusSrcTran) Status for Destination Transaction Interrupts (StatusDstTran) Status for Error Interrupts (StatusErr) Mask for Transfer Interrupts (MaskTfr) Mask for Block Interrupts (MaskBlock) Mask for Source Transaction Interrupts (MaskSrcTran) Mask for Destination Transaction Interrupts (MaskDstTran) Mask for Error Interrupts (MaskErr) Clear for Transfer Interrupts (ClearTfr) Clear for Block Interrupts (ClearBlock) Clear for Source Transaction Interrupts (ClearSrcTran) Clear for Destination Transaction Interrupts (ClearDstTran) Clear for Error Interrupts (ClearErr) Combined Status (StatusInt) DMA Configuration (DmaCfgReg) DMA Channel Enable (ChEnReg) Global DMA Configuration (GLOBAL_CFG)
UART MMIO Divisor Latch Low (DLL) Transmit Holding (THR) Receive Buffer (RBR) Interrupt Enable (IER) Divisor Latch High (DLH) FIFO Control (FCR) Interrupt Control (IIR) Line Control Register (LCR) Modem Control Register (MCR) Line Status Register (LSR) Modem Status Register (MSR) Scratchpad Register (SCR) Shadow Receive Buffer Register and Shadow Transmit Holding Register 0 (SRBR_STHR0) Shadow Receive Buffer Register and Shadow Transmit Holding Register 1 (SRBR_STHR1) Shadow Receive Buffer Register and Shadow Transmit Holding Register 2 (SRBR_STHR2) Shadow Receive Buffer Register and Shadow Transmit Holding Register 3 (SRBR_STHR3) Shadow Receive Buffer Register and Shadow Transmit Holding Register 4 (SRBR_STHR4) Shadow Receive Buffer Register and Shadow Transmit Holding Register 5 (SRBR_STHR5) Shadow Receive Buffer Register and Shadow Transmit Holding Register 6 (SRBR_STHR6) Shadow Receive Buffer Register and Shadow Transmit Holding Register 7 (SRBR_STHR7) Shadow Receive Buffer Register and Shadow Transmit Holding Register 8 (SRBR_STHR8) Shadow Receive Buffer Register and Shadow Transmit Holding Register 9 (SRBR_STHR9) Shadow Receive Buffer Register and Shadow Transmit Holding Register 10 (SRBR_STHR10) Shadow Receive Buffer Register and Shadow Transmit Holding Register 11 (SRBR_STHR11) Shadow Receive Buffer Register and Shadow Transmit Holding Register 12 (SRBR_STHR12) Shadow Receive Buffer Register and Shadow Transmit Holding Register 13 (SRBR_STHR13) Shadow Receive Buffer Register and Shadow Transmit Holding Register 14 (SRBR_STHR14) Shadow Receive Buffer Register and Shadow Transmit Holding Register 15 (SRBR_STHR15) FIFO Access Register (FAR) Transmit FIFO Read (TFR) Receive FIFO Write (RFW) UART Status Register (USR) Transmit FIFO Level (TFL) Receive FIFO Level (RFL) Software Reset Register (SRR) Shadow Request to Send (SRTS) Shadow Break Control Bit (SBCR) Shadow DMA Mode (SDMAM) Shadow FIFO Enable (SFE) Shadow RCVR Trigger (SRT) Shadow TX Empty Trigger. (STET) Halt TX (HTX) DMA Software Acknowledge (DMASA) Component Parameter Register (CPR) UART Component Version (UCV) Component Type Register (CTR)
USB MMIO Capability Registers Length (CAPLENGTH) Host Controller Interface Version Number (HCIVERSION) Structural Parameters 1 (HCSPARAMS1) Structural Parameters 2 (HCSPARAMS2) Structural Parameters 3 (HCSPARAMS3) Capability Parameters (HCCPARAMS) Doorbell Offset (DBOFF) Runtime Register Space Offset (RTSOFF) USB Command (USBCMD) USB Status (USBSTS) Page Size (PAGESIZE) Device Notification Control (DNCTRL) Command Ring Low (CRCR_LO) Command Ring High (CRCR_HI) Device Context Base Address Array Pointer Low (DCBAAP_LO) Device Context Base Address Array Pointer High (DCBAAP_HI) Configure Reg (CONFIG) Port Status AndControl USB2 (PORTSC1) Port Power Management Status Aand Control USB2 (PORTPMSC1) Port X Hardware LPM Control Register (PORTHLPMC1) Port Status AndControl USB2 (PORTSC2) Port Power Management Status Aand Control USB2 (PORTPMSC2) Port X Hardware LPM Control Register (PORTHLPMC2) Port Status AndControl USB2 (PORTSC3) Port Power Management Status Aand Control USB2 (PORTPMSC3) Port X Hardware LPM Control Register (PORTHLPMC3) Port Status AndControl USB2 (PORTSC4) Port Power Management Status Aand Control USB2 (PORTPMSC4) Port X Hardware LPM Control Register (PORTHLPMC4) Port Status AndControl USB2 (PORTSC5) Port Power Management Status Aand Control USB2 (PORTPMSC5) Port X Hardware LPM Control Register (PORTHLPMC5) Port Status AndControl USB2 (PORTSC6) Port Power Management Status Aand Control USB2 (PORTPMSC6) Port X Hardware LPM Control Register (PORTHLPMC6) Port Status AndControl USB2 (PORTSC7) Port Power Management Status Aand Control USB2 (PORTPMSC7) Port X Hardware LPM Control Register (PORTHLPMC7) Port Status AndControl USB2 (PORTSC8) Port Power Management Status Aand Control USB2 (PORTPMSC8) Port X Hardware LPM Control Register (PORTHLPMC8) Port Status And Control USB2 (PORTSC9) Port Power Management Status Aand Control USB2 (PORTPMSC9) Port X Hardware LPM Control Register (PORTHLPMC9) Port Status AndControl USB2 (PORTSC10) Port Power Management Status Aand Control USB2 (PORTPMSC10) Port X Hardware LPM Control Register (PORTHLPMC10) Port Status AndControl USB2 (PORTSC11) Port Power Management Status Aand Control USB2 (PORTPMSC11) Port X Hardware LPM Control Register (PORTHLPMC11) Port Status AndControl USB2 (PORTSC12) Port Power Management Status Aand Control USB2 (PORTPMSC12) Port X Hardware LPM Control Register (PORTHLPMC12) Port Status AndControl USB2 (PORTSC13) Port Power Management Status Aand Control USB2 (PORTPMSC13) Port X Hardware LPM Control Register (PORTHLPMC13) Port Status AndControl USB2 (PORTSC14) Port Power Management Status Aand Control USB2 (PORTPMSC14) Port X Hardware LPM Control Register (PORTHLPMC14) Port Status And Control USB3 (PORTSC17) Port Power Management Status And Control USB3 (PORTPMSC17) USB3 Port Link Info (PORTLI17) PORT SOFT ERR CNT (PORTSOFTERRX17) Port Status And Control USB3 (PORTSC18) Port Power Management Status And Control USB3 (PORTPMSC18) USB3 Port Link Info (PORTLI18) Port Status And Control USB3 (PORTSC19) Port Power Management Status And Control USB3 (PORTPMSC19) USB3 Port Link Info (PORTLI19) Port Status And Control USB3 (PORTSC20) Port Power Management Status And Control USB3 (PORTPMSC20) USB3 Port Link Info (PORTLI20) Port Status And Control USB3 (PORTSC21) Port Power Management Status And Control USB3 (PORTPMSC21) USB3 Port Link Info (PORTLI21) Port Status And Control USB3 (PORTSC22) Port Power Management Status And Control USB3 (PORTPMSC22) USB3 Port Link Info (PORTLI22) Port Status And Control USB3 (PORTSC23) Port Power Management Status And Control USB3 (PORTPMSC23) USB3 Port Link Info (PORTLI23) Port Status And Control USB3 (PORTSC24) Port Power Management Status And Control USB3 (PORTPMSC24) USB3 Port Link Info (PORTLI24) Port Status And Control USB3 (PORTSC25) Port Power Management Status And Control USB3 (PORTPMSC25) USB3 Port Link Info (PORTLI25) Port Status And Control USB3 (PORTSC26) Port Power Management Status And Control USB3 (PORTPMSC26) USB3 Port Link Info (PORTLI26) Microframe Index (RTMFINDEX) Interrupter Management (IMAN0) Interrupter Moderation (IMOD0) Event Ring Segment Table Size (ERSTSZ0) Event Ring Segment Table Base Address Low (ERSTBA_LO0) Event Ring Segment Table Base Address High (ERSTBA_HI0) Event Ring Dequeue Pointer Low (ERDP_LO0) Event Ring Dequeue Pointer High (ERDP_HI0) Interrupter Management (IMAN1) Interrupter Moderation (IMOD1) Event Ring Segment Table Size (ERSTSZ1) Event Ring Segment Table Base Address Low (ERSTBA_LO1) Event Ring Segment Table Base Address High (ERSTBA_HI1) Event Ring Dequeue Pointer Low (ERDP_LO1) Event Ring Dequeue Pointer High (ERDP_HI1) Interrupter Management (IMAN2) Interrupter Moderation (IMOD2) Event Ring Segment Table Size (ERSTSZ2) Event Ring Segment Table Base Address Low (ERSTBA_LO2) Event Ring Segment Table Base Address High (ERSTBA_HI2) Event Ring Dequeue Pointer Low (ERDP_LO2) Event Ring Dequeue Pointer High (ERDP_HI2) Interrupter Management (IMAN3) Interrupter Moderation (IMOD3) Event Ring Segment Table Size (ERSTSZ3) Event Ring Segment Table Base Address Low (ERSTBA_LO3) Event Ring Segment Table Base Address High (ERSTBA_HI3) Event Ring Dequeue Pointer Low (ERDP_LO3) Event Ring Dequeue Pointer High (ERDP_HI3) Interrupter Management (IMAN4) Interrupter Moderation (IMOD4) Event Ring Segment Table Size (ERSTSZ4) Event Ring Segment Table Base Address Low (ERSTBA_LO4) Event Ring Segment Table Base Address High (ERSTBA_HI4) Event Ring Dequeue Pointer Low (ERDP_LO4) Event Ring Dequeue Pointer High (ERDP_HI4) Interrupter Management (IMAN5) Interrupter Moderation (IMOD5) Event Ring Segment Table Size (ERSTSZ5) Event Ring Segment Table Base Address Low (ERSTBA_LO5) Event Ring Segment Table Base Address High (ERSTBA_HI5) Event Ring Dequeue Pointer Low (ERDP_LO5) Event Ring Dequeue Pointer High (ERDP_HI5) Interrupter Management (IMAN6) Interrupter Moderation (IMOD6) Event Ring Segment Table Size (ERSTSZ6) Event Ring Segment Table Base Address Low (ERSTBA_LO6) Event Ring Segment Table Base Address High (ERSTBA_HI6) Event Ring Dequeue Pointer Low (ERDP_LO6) Event Ring Dequeue Pointer High (ERDP_HI6) Interrupter Management (IMAN7) Interrupter Moderation (IMOD7) Event Ring Segment Table Size (ERSTSZ7) Event Ring Segment Table Base Address Low (ERSTBA_LO7) Event Ring Segment Table Base Address High (ERSTBA_HI7) Event Ring Dequeue Pointer Low (ERDP_LO7) Event Ring Dequeue Pointer High (ERDP_HI7) Door Bell (DB0) Door Bell (DB1) Door Bell (DB2) Door Bell (DB3) Door Bell (DB4) Door Bell (DB5) Door Bell (DB6) Door Bell (DB7) Door Bell (DB8) Door Bell (DB9) Door Bell (DB10) Door Bell (DB11) Door Bell (DB12) Door Bell (DB13) Door Bell (DB14) Door Bell (DB15) Door Bell (DB16) Door Bell (DB17) Door Bell (DB18) Door Bell (DB19) Door Bell (DB20) Door Bell (DB21) Door Bell (DB22) Door Bell (DB23) Door Bell (DB30) Door Bell (DB31) XECP SUPP USB2_1 (XECP_SUPP_USB2_1) XECP SUPP USB3_3 (XECP_SUPP_USB2_3) XECP SUPP USB2_4 Full Speed (XECP_SUPP_USB2_4) XECP_SUPP USB2_5 Low Speed (XECP_SUPP_USB2_5) XECP SUPP USB2_6 High Speed (XECP_SUPP_USB2_6) XECP SUPP USB3_0 (XECP_SUPP_USB3_0) XECP SUPP USB3_1 (XECP_SUPP_USB3_1) XECP SUPP USB3_2 (XECP_SUPP_USB3_2) XECP SUPP USB3_3 (XECP_SUPP_USB3_3) XECP SUPP USB3_4 (XECP_SUPP_USB3_4) XECP SUPP USB3_5 (XECP_SUPP_USB3_5) XECP SUPP USB3_6 (XECP_SUPP_USB3_6) XECP SUPP USB3_7 (XECP_SUPP_USB3_7) Host Control Scheduler (HOST_CTRL_SCH_REG) Power Management Control (PMCTRL_REG) Host Controller Misc Reg (HOST_CTRL_MISC_REG) Super Speed Port Enable (SSPE_REG) AUX Power Management Control (AUX_CTRL_REG1) SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG) USB2 Port Link Control 1 (USB2_LINK_MGR_CTRL_REG1) USB2 Port Link Control 2 (USB2_LINK_MGR_CTRL_REG2) USB2 Port Link Control 3 (USB2_LINK_MGR_CTRL_REG3) USB2 Port Link Control 4 (USB2_LINK_MGR_CTRL_REG4) Power Scheduler Control-0 (PWR_SCHED_CTRL0) Power Scheduler Control-1 (PWR_SCHED_CTRL2) AUX Power Management Control (AUX_CTRL_REG2) USB2 PHY Power Management Control (USB2_PHY_PMC) XHCI Aux Clock Control Register (XHCI_AUX_CCR) XHC Latency Tolerance Parameters LTV Control (XLTP_LTV1) XHC Latency Tolerance Parameters High Idle Time Control (XLTP_HITC) XHC Latency Tolerance Parameters Medium Idle Time Control (XLTP_MITC) XHC Latency Tolerance Parameters Low Idle Time Control (XLTP_LITC) LFPS On Count (LFPSONCOUNT_REG) USB2 Power Management Control (USB2PMCTRL_REG) USB Legacy Support Capability (USBLEGSUP) USB Legacy Support Control Status (USBLEGCTLSTS) Port Disable Override Capability Register (PDO_CAPABILITY) USB 2.0 Port Disable Override (USB2PDO) USB 3.0 Port Disable Override (USB3PDO) Command Reg (CMD_MMIO) Device Status (STS_MMIO) Revision ID (RID_MMIO) Programming Interface (PI_MMIO) Sub Class Code (SCC_MMIO) Base Class Code (BCC_MMIO) Cache Line Size (CLS_MMIO) Master Latency Timer (MLT_MMIO) Header Type (HT_MMIO) Memory Base Address (MBAR_MMIO) USB Subsystem Vendor ID (SSVID_MMIO) USB Subsystem ID (SSID_MMIO) Capabilities Pointer (CAP_PTR_MMIO) Interrupt Line (ILINE_MMIO) Interrupt Pin (IPIN_MMIO) Serial Bus Release Number (SBRN_MMIO) Frame Length Adjustment (FLADJ_MMIO) Best Effort Service Latency (BESL_MMIO) PCI Power Management Capability ID (PM_CID_MMIO) Next Item Pointer 1 (PM_NEXT_MMIO) Power Management Capabilities (PM_CAP_MMIO) Power Management Control/Status (PM_CS_MMIO) Message Signaled Interrupt CID (MSI_CID_MMIO) Next Item Pointer (MSI_NEXT_MMIO) Message Signaled Interrupt Message Control (MSI_MCTL_MMIO) Message Signaled Interrupt Message Address (MSI_MAD_MMIO) Message Signaled Interrupt Upper Address (MSI_MUAD_MMIO) Message Signaled Interrupt Message Data (MSI_MD_MMIO) DAP USB 2.0 Port <N> Control 0 (DAP_USB2_PORT_CONTROL_0_REG_0_MMIO) DAP USB 2.0 Port <N> Control 1 (DAP_USB2_PORT_CONTROL_1_REG_0_MMIO) DAP USB 2.0 Port <N> Status (DAP_USB2_PORT_STATUS_REG_0_MMIO) DAP USB 3.0 Port <N> Control 0 (DAP_ESS_PORT_CONTROL_0_REG_0_MMIO) DAP USB 3.0 Port <N> Control 1 (DAP_ESS_PORT_CONTROL_1_REG_0_MMIO) DAP USB 3.0 Port <N> Status (DAP_ESS_PORT_STATUS_REG_0_MMIO) GLOBAL TIME SYNC CAP REG (GLOBAL_TIME_SYNC_CAP_REG) GLOBAL TIME SYNC CTRL REG (GLOBAL_TIME_SYNC_CTRL_REG) MICROFRAME TIME REG (MICROFRAME_TIME_REG) Global Time Value (Low Register) (GLOBAL_TIME_LOW_REG) GLOBAL TIME HI REG (GLOBAL_TIME_HI_REG) XHCI USB2 Overcurrent Pin Mapping (U2OCM1) XHCI USB2 Overcurrent Pin Mapping (U2OCM2) XHCI USB2 Overcurrent Pin Mapping (U2OCM3) XHCI USB2 Overcurrent Pin Mapping (U2OCM4) XHCI USB2 Overcurrent Pin Mapping (U2OCM5) XHCI USB2 Overcurrent Pin Mapping (U2OCM6) XHCI USB2 Overcurrent Pin Mapping (U2OCM7) XHCI USB2 Overcurrent Pin Mapping (U2OCM8) XHCI USB2 Overcurrent Pin Mapping (U2OCM9) XHCI USB2 Overcurrent Pin Mapping (U2OCM10) XHCI USB2 Overcurrent Pin Mapping (U2OCM11) XHCI USB2 Overcurrent Pin Mapping (U2OCM12) XHCI USB3 Overcurrent Pin Mapping (U3OCM1) XHCI USB3 Overcurrent Pin Mapping (U3OCM2) XHCI USB3 Overcurrent Pin Mapping (U3OCM3) XHCI USB3 Overcurrent Pin Mapping (U3OCM4) XHCI USB3 Overcurrent Pin Mapping (U3OCM5) XHCI USB3 Overcurrent Pin Mapping (U3OCM6) XHCI USB3 Overcurrent Pin Mapping (U3OCM7) XHCI USB3 Overcurrent Pin Mapping (U3OCM8) XHCI USB3 Overcurrent Pin Mapping (U3OCM9) XHCI USB3 Overcurrent Pin Mapping (U3OCM10) XHCI USB3 Overcurrent Pin Mapping (U3OCM11) XHCI USB3 Overcurrent Pin Mapping (U3OCM12)

Intel® High Definition Audio MMIO Registers

Summary of Bus: (), Device: (), Function: (), Type: (MEM)

Offset

Size (Bytes)

Register Name (Register Symbol)

Scope

Default Value

0h

2

Global Capabilities (GCAP)

Package

9A01h

2h

1

Minor Version (VMIN)

Package

00h

3h

1

Major Version (VMAJ)

Package

01h

4h

2

Output Payload Capability (OUTPAY)

Package

003Ch

6h

2

Input Payload Capability (INPAY)

Package

001Dh

8h

4

Global Control (GCTL)

Package

00000000h

ch

1

Wake Enable (WAKEEN)

Package

00h

eh

1

Wake Status (WAKESTS)

Package

00h

10h

2

Global Status (GSTS)

Package

0000h

12h

2

Global Capabilities 2 (GCAP2)

Package

0000h

14h

2

Linked List Capabilities Header (LLCH)

Package

0C00h

18h

2

Output Stream Payload Capability (OUTSTRMPAY)

Package

0030h

1ah

2

Input Stream Payload Capability (INSTRMPAY)

Package

0018h

20h

4

Interrupt Control (INTCTL)

Package

00000000h

24h

4

Interrupt Status (INTSTS)

Package

00000000h

30h

4

Wall Clock Counter (WALCLK)

Package

00000000h

38h

4

Stream Synchronization (SSYNC)

Package

00000000h

40h

4

CORB Lower Base Address (CORBLBASE)

Package

00000000h

44h

4

CORB Upper Base Address (CORBUBASE)

Package

00000000h

48h

2

CORB Write Pointer (CORBWP)

Package

0000h

4ah

2

CORB Read Pointer (CORBRP)

Package

0000h

4ch

1

CORB Control (CORBCTL)

Package

00h

4dh

1

CORB Status (CORBSTS)

Package

00h

4eh

1

CORB Size (CORBSIZE)

Package

42h

60h

4

Immediate Command (IC)

Package

00000000h

64h

4

Immediate Response (IR)

Package

00000000h

68h

2

Immediate Command Status (ICS)

Package

0000h

70h

4

DMA Position Lower Base Address (DPLBASE)

Package

00000000h

74h

4

DMA Position Upper Base Address (DPUBASE)

Package

00000000h

80h

1

Input Stream Descriptor x Control (ISD0CTL_​B0)

Package

00h

82h

1

Input Stream Descriptor x Control (ISD0CTL_​B2)

Package

04h

83h

1

Input Stream Descriptor x Status (ISD0STS)

Package

00h

84h

4

Input Stream Descriptor x Link Position in Buffer (ISD0LPIB)

Package

00000000h

88h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD0CBL)

Package

00000000h

8ch

2

Input Stream Descriptor x Last Valid Index (ISD0LVI)

Package

0000h

8eh

1

Input Stream Descriptor x FIFO Eviction Watermark (ISD0FIFOW)

Package

04h

90h

2

Input Stream Descriptor x FIFO Size (ISD0FIFOS)

Package

0000h

92h

2

Input Stream Descriptor x Format (ISD0FMT)

Package

0000h

98h

4

Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD0BDLPLBA)

Package

00000000h

9ch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD0BDLPUBA)

Package

00000000h

a0h

1

Input Stream Descriptor x Control (ISD1CTL_​B0)

Package

00h

a2h

1

Input Stream Descriptor x Control (ISD1CTL_​B2)

Package

00h

a3h

1

Input Stream Descriptor x Status (ISD1STS)

Package

00h

a4h

4

Input Stream Descriptor x Link Position in Buffer (ISD1LPIB)

Package

00000000h

a8h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD1CBL)

Package

00000000h

ach

2

Input Stream Descriptor x Last Valid Index (ISD1LVI)

Package

0000h

aeh

1

Input Stream Descriptor x FIFO Eviction Watermark (ISD1FIFOW)

Package

00h

b0h

2

Input Stream Descriptor x FIFO Size (ISD1FIFOS)

Package

0000h

b2h

2

Input Stream Descriptor x Format (ISD1FMT)

Package

0000h

b8h

4

Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD1BDLPLBA)

Package

00000000h

bch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD1BDLPUBA)

Package

00000000h

c0h

1

Input Stream Descriptor x Control (ISD2CTL_​B0)

Package

00h

c2h

1

Input Stream Descriptor x Control (ISD2CTL_​B2)

Package

00h

c3h

1

Input Stream Descriptor x Status (ISD2STS)

Package

00h

c4h

4

Input Stream Descriptor x Link Position in Buffer (ISD2LPIB)

Package

00000000h

c8h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD2CBL)

Package

00000000h

cch

2

Input Stream Descriptor x Last Valid Index (ISD2LVI)

Package

0000h

ceh

1

Input Stream Descriptor x FIFO Eviction Watermark (ISD2FIFOW)

Package

00h

d0h

2

Input Stream Descriptor x FIFO Size (ISD2FIFOS)

Package

0000h

d2h

2

Input Stream Descriptor x Format (ISD2FMT)

Package

0000h

d8h

4

Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD2BDLPLBA)

Package

00000000h

dch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD2BDLPUBA)

Package

00000000h

e0h

1

Input Stream Descriptor x Control (ISD3CTL_​B0)

Package

00h

e2h

1

Input Stream Descriptor x Control (ISD3CTL_​B2)

Package

00h

e3h

1

Input Stream Descriptor x Status (ISD3STS)

Package

00h

e4h

4

Input Stream Descriptor x Link Position in Buffer (ISD3LPIB)

Package

00000000h

e8h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD3CBL)

Package

00000000h

ech

2

Input Stream Descriptor x Last Valid Index (ISD3LVI)

Package

0000h

eeh

1

Input Stream Descriptor x FIFO Eviction Watermark (ISD3FIFOW)

Package

00h

f0h

2

Input Stream Descriptor x FIFO Size (ISD3FIFOS)

Package

0000h

f2h

2

Input Stream Descriptor x Format (ISD3FMT)

Package

0000h

f8h

4

Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD3BDLPLBA)

Package

00000000h

fch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD3BDLPUBA)

Package

00000000h

100h

1

Input Stream Descriptor x Control (ISD4CTL_​B0)

Package

00h

102h

1

Input Stream Descriptor x Control (ISD4CTL_​B2)

Package

00h

103h

1

Input Stream Descriptor x Status (ISD4STS)

Package

00h

104h

4

Input Stream Descriptor x Link Position in Buffer (ISD4LPIB)

Package

00000000h

108h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD4CBL)

Package

00000000h

10ch

2

Input Stream Descriptor x Last Valid Index (ISD4LVI)

Package

0000h

10eh

1

Input Stream Descriptor x FIFO Eviction Watermark (ISD4FIFOW)

Package

00h

110h

2

Input Stream Descriptor x FIFO Size (ISD4FIFOS)

Package

0000h

112h

2

Input Stream Descriptor x Format (ISD4FMT)

Package

0000h

118h

4

Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD4BDLPLBA)

Package

00000000h

11ch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD4BDLPUBA)

Package

00000000h

120h

1

Input Stream Descriptor x Control (ISD5CTL_​B0)

Package

00h

122h

1

Input Stream Descriptor x Control (ISD5CTL_​B2)

Package

00h

123h

1

Input Stream Descriptor x Status (ISD5STS)

Package

00h

128h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD5CBL)

Package

00000000h

12ch

2

Input Stream Descriptor x Last Valid Index (ISD5LVI)

Package

0000h

12eh

1

Input Stream Descriptor x FIFO Eviction Watermark (ISD5FIFOW)

Package

00h

130h

2

Input Stream Descriptor x FIFO Size (ISD5FIFOS)

Package

0000h

132h

2

Input Stream Descriptor x Format (ISD5FMT)

Package

0000h

13ch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD5BDLPUBA)

Package

00000000h

140h

1

Input Stream Descriptor x Control (ISD6CTL_​B0)

Package

00h

142h

1

Input Stream Descriptor x Control (ISD6CTL_​B2)

Package

00h

143h

1

Input Stream Descriptor x Status (ISD6STS)

Package

00h

144h

4

Input Stream Descriptor x Link Position in Buffer (ISD6LPIB)

Package

00000000h

148h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD6CBL)

Package

00000000h

14ch

2

Input Stream Descriptor x Last Valid Index (ISD6LVI)

Package

0000h

14eh

1

Input Stream Descriptor x FIFO Eviction Watermark (ISD6FIFOW)

Package

00h

150h

2

Input Stream Descriptor x FIFO Size (ISD6FIFOS)

Package

0000h

152h

2

Input Stream Descriptor x Format (ISD6FMT)

Package

0000h

158h

4

Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD6BDLPLBA)

Package

00000000h

15ch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD6BDLPUBA)

Package

00000000h

160h

1

Input Stream Descriptor x Control (ISD7CTL_​B0)

Package

00h

162h

1

Input Stream Descriptor x Control (ISD7CTL_​B2)

Package

00h

163h

1

Input Stream Descriptor x Status (ISD7STS)

Package

00h

164h

4

Input Stream Descriptor x Link Position in Buffer (ISD7LPIB)

Package

00000000h

168h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD7CBL)

Package

00000000h

16ch

2

Input Stream Descriptor x Last Valid Index (ISD7LVI)

Package

0000h

16eh

1

Input Stream Descriptor x FIFO Eviction Watermark (ISD7FIFOW)

Package

00h

170h

2

Input Stream Descriptor x FIFO Size (ISD7FIFOS)

Package

0000h

172h

2

Input Stream Descriptor x Format (ISD7FMT)

Package

0000h

178h

4

Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD7BDLPLBA)

Package

00000000h

17ch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD7BDLPUBA)

Package

00000000h

180h

1

Input Stream Descriptor x Control (ISD8CTL_​B0)

Package

00h

182h

1

Input Stream Descriptor x Control (ISD8CTL_​B2)

Package

00h

183h

1

Input Stream Descriptor x Status (ISD8STS)

Package

00h

184h

4

Input Stream Descriptor x Link Position in Buffer (ISD8LPIB)

Package

00000000h

188h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD8CBL)

Package

00000000h

18ch

2

Input Stream Descriptor x Last Valid Index (ISD8LVI)

Package

0000h

18eh

1

Input Stream Descriptor x FIFO Eviction Watermark (ISD8FIFOW)

Package

00h

190h

2

Input Stream Descriptor x FIFO Size (ISD8FIFOS)

Package

0000h

192h

2

Input Stream Descriptor x Format (ISD8FMT)

Package

0000h

19ch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD8BDLPUBA)

Package

00000000h

1a0h

1

Input Stream Descriptor x Control (ISD9CTL_​B0)

Package

00h

1a2h

1

Input Stream Descriptor x Control (ISD9CTL_​B2)

Package

00h

1a3h

1

Input Stream Descriptor x Status (ISD9STS)

Package

00h

1a8h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD9CBL)

Package

00000000h

1ach

2

Input Stream Descriptor x Last Valid Index (ISD9LVI)

Package

0000h

1aeh

1

Input Stream Descriptor x FIFO Eviction Watermark (ISD9FIFOW)

Package

00h

1b0h

2

Input Stream Descriptor x FIFO Size (ISD9FIFOS)

Package

0000h

1b2h

2

Input Stream Descriptor x Format (ISD9FMT)

Package

0000h

1b8h

4

Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD9BDLPLBA)

Package

00000000h

1bch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD9BDLPUBA)

Package

00000000h

1c0h

1

Output Stream Descriptor x Control (OSD0CTL_​B0)

Package

00h

1c2h

1

Output Stream Descriptor x Control (OSD0CTL_​B2)

Package

04h

1c3h

1

Output Stream Descriptor x Status (OSD0STS)

Package

00h

1c4h

4

Output Stream Descriptor x Link Position in Buffer (OSD0LPIB)

Package

00000000h

1c8h

4

Output Stream Descriptor x Cyclic Buffer Length (OSD0CBL)

Package

00000000h

1cch

2

Output Stream Descriptor x Last Valid Index (OSD0LVI)

Package

0000h

1ceh

1

Output Stream Descriptor x FIFO Eviction Watermark (OSD0FIFOW)

Package

04h

1d0h

2

Output Stream Descriptor x FIFO Size (OSD0FIFOS)

Package

0000h

1d2h

2

Output Stream Descriptor x Format (OSD0FMT)

Package

0000h

1d8h

4

Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD0BDLPLBA)

Package

00000000h

1dch

4

Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD0BDLPUBA)

Package

00000000h

1e0h

1

Output Stream Descriptor x Control (OSD1CTL_​B0)

Package

00h

1e2h

1

Output Stream Descriptor x Control (OSD1CTL_​B2)

Package

00h

1e3h

1

Output Stream Descriptor x Status (OSD1STS)

Package

00h

1e4h

4

Output Stream Descriptor x Link Position in Buffer (OSD1LPIB)

Package

00000000h

1e8h

4

Output Stream Descriptor x Cyclic Buffer Length (OSD1CBL)

Package

00000000h

1ech

2

Output Stream Descriptor x Last Valid Index (OSD1LVI)

Package

0000h

1eeh

1

Output Stream Descriptor x FIFO Eviction Watermark (OSD1FIFOW)

Package

00h

1f0h

2

Output Stream Descriptor x FIFO Size (OSD1FIFOS)

Package

0000h

1f2h

2

Output Stream Descriptor x Format (OSD1FMT)

Package

0000h

1f8h

4

Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD1BDLPLBA)

Package

00000000h

1fch

4

Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD1BDLPUBA)

Package

00000000h

200h

1

Output Stream Descriptor x Control (OSD2CTL_​B0)

Package

00h

202h

1

Output Stream Descriptor x Control (OSD2CTL_​B2)

Package

00h

203h

1

Output Stream Descriptor x Status (OSD2STS)

Package

00h

204h

4

Output Stream Descriptor x Link Position in Buffer (OSD2LPIB)

Package

00000000h

208h

4

Output Stream Descriptor x Cyclic Buffer Length (OSD2CBL)

Package

00000000h

20ch

2

Output Stream Descriptor x Last Valid Index (OSD2LVI)

Package

0000h

20eh

1

Output Stream Descriptor x FIFO Eviction Watermark (OSD2FIFOW)

Package

00h

210h

2

Output Stream Descriptor x FIFO Size (OSD2FIFOS)

Package

0000h

212h

2

Output Stream Descriptor x Format (OSD2FMT)

Package

0000h

218h

4

Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD2BDLPLBA)

Package

00000000h

21ch

4

Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD2BDLPUBA)

Package

00000000h

220h

1

Output Stream Descriptor x Control (OSD3CTL_​B0)

Package

00h

222h

1

Output Stream Descriptor x Control (OSD3CTL_​B2)

Package

00h

223h

1

Output Stream Descriptor x Status (OSD3STS)

Package

00h

224h

4

Output Stream Descriptor x Link Position in Buffer (OSD3LPIB)

Package

00000000h

228h

4

Output Stream Descriptor x Cyclic Buffer Length (OSD3CBL)

Package

00000000h

22ch

2

Output Stream Descriptor x Last Valid Index (OSD3LVI)

Package

0000h

22eh

1

Output Stream Descriptor x FIFO Eviction Watermark (OSD3FIFOW)

Package

00h

230h

2

Output Stream Descriptor x FIFO Size (OSD3FIFOS)

Package

0000h

232h

2

Output Stream Descriptor x Format (OSD3FMT)

Package

0000h

238h

4

Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD3BDLPLBA)

Package

00000000h

23ch

4

Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD3BDLPUBA)

Package

00000000h

240h

1

Output Stream Descriptor x Control (OSD4CTL_​B0)

Package

00h

242h

1

Output Stream Descriptor x Control (OSD4CTL_​B2)

Package

00h

243h

1

Output Stream Descriptor x Status (OSD4STS)

Package

00h

244h

4

Output Stream Descriptor x Link Position in Buffer (OSD4LPIB)

Package

00000000h

248h

4

Output Stream Descriptor x Cyclic Buffer Length (OSD4CBL)

Package

00000000h

24ch

2

Output Stream Descriptor x Last Valid Index (OSD4LVI)

Package

0000h

24eh

1

Output Stream Descriptor x FIFO Eviction Watermark (OSD4FIFOW)

Package

00h

250h

2

Output Stream Descriptor x FIFO Size (OSD4FIFOS)

Package

0000h

252h

2

Output Stream Descriptor x Format (OSD4FMT)

Package

0000h

258h

4

Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD4BDLPLBA)

Package

00000000h

25ch

4

Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD4BDLPUBA)

Package

00000000h

260h

1

Output Stream Descriptor x Control (OSD5CTL_​B0)

Package

00h

262h

1

Output Stream Descriptor x Control (OSD5CTL_​B2)

Package

00h

263h

1

Output Stream Descriptor x Status (OSD5STS)

Package

00h

264h

4

Output Stream Descriptor x Link Position in Buffer (OSD5LPIB)

Package

00000000h

268h

4

Output Stream Descriptor x Cyclic Buffer Length (OSD5CBL)

Package

00000000h

26ch

2

Output Stream Descriptor x Last Valid Index (OSD5LVI)

Package

0000h

26eh

1

Output Stream Descriptor x FIFO Eviction Watermark (OSD5FIFOW)

Package

00h

270h

2

Output Stream Descriptor x FIFO Size (OSD5FIFOS)

Package

0000h

272h

2

Output Stream Descriptor x Format (OSD5FMT)

Package

0000h

278h

4

Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD5BDLPLBA)

Package

00000000h

27ch

4

Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD5BDLPUBA)

Package

00000000h

280h

1

Output Stream Descriptor x Control (OSD6CTL_​B0)

Package

00h

282h

1

Output Stream Descriptor x Control (OSD6CTL_​B2)

Package

00h

283h

1

Output Stream Descriptor x Status (OSD6STS)

Package

00h

284h

4

Output Stream Descriptor x Link Position in Buffer (OSD6LPIB)

Package

00000000h

288h

4

Output Stream Descriptor x Cyclic Buffer Length (OSD6CBL)

Package

00000000h

28ch

2

Output Stream Descriptor x Last Valid Index (OSD6LVI)

Package

0000h

28eh

1

Output Stream Descriptor x FIFO Eviction Watermark (OSD6FIFOW)

Package

00h

290h

2

Output Stream Descriptor x FIFO Size (OSD6FIFOS)

Package

0000h

292h

2

Output Stream Descriptor x Format (OSD6FMT)

Package

0000h

298h

4

Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD6BDLPLBA)

Package

00000000h

29ch

4

Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD6BDLPUBA)

Package

00000000h

2a0h

1

Output Stream Descriptor x Control (OSD7CTL_​B0)

Package

00h

2a2h

1

Output Stream Descriptor x Control (OSD7CTL_​B2)

Package

00h

2a3h

1

Output Stream Descriptor x Status (OSD7STS)

Package

00h

2a4h

4

Output Stream Descriptor x Link Position in Buffer (OSD7LPIB)

Package

00000000h

2a8h

4

Output Stream Descriptor x Cyclic Buffer Length (OSD7CBL)

Package

00000000h

2ach

2

Output Stream Descriptor x Last Valid Index (OSD7LVI)

Package

0000h

2aeh

1

Output Stream Descriptor x FIFO Eviction Watermark (OSD7FIFOW)

Package

00h

2b0h

2

Output Stream Descriptor x FIFO Size (OSD7FIFOS)

Package

0000h

2b2h

2

Output Stream Descriptor x Format (OSD7FMT)

Package

0000h

2b8h

4

Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD7BDLPLBA)

Package

00000000h

2bch

4

Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD7BDLPUBA)

Package

00000000h

2c0h

1

Output Stream Descriptor x Control (OSD8CTL_​B0)

Package

00h

2c2h

1

Output Stream Descriptor x Control (OSD8CTL_​B2)

Package

00h

2c3h

1

Output Stream Descriptor x Status (OSD8STS)

Package

00h

2c4h

4

Output Stream Descriptor x Link Position in Buffer (OSD8LPIB)

Package

00000000h

2c8h

4

Output Stream Descriptor x Cyclic Buffer Length (OSD8CBL)

Package

00000000h

2cch

2

Output Stream Descriptor x Last Valid Index (OSD8LVI)

Package

0000h

2ceh

1

Output Stream Descriptor x FIFO Eviction Watermark (OSD8FIFOW)

Package

00h

2d0h

2

Output Stream Descriptor x FIFO Size (OSD8FIFOS)

Package

0000h

2d2h

2

Output Stream Descriptor x Format (OSD8FMT)

Package

0000h

2d8h

4

Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD8BDLPLBA)

Package

00000000h

2dch

4

Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD8BDLPUBA)

Package

00000000h

500h

4

DMA Resume Capability Header (DRSMCH)

Package

00050700h

504h

4

DMA Resume Control (DRSMCTL)

Package

00000000h

508h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD0DPIBR)

Package

00000000h

510h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD1DPIBR)

Package

00000000h

518h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD2DPIBR)

Package

00000000h

520h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD3DPIBR)

Package

00000000h

528h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD4DPIBR)

Package

00000000h

530h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD5DPIBR)

Package

00000000h

538h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD6DPIBR)

Package

00000000h

540h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD7DPIBR)

Package

00000000h

548h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD8DPIBR)

Package

00000000h

550h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD9DPIBR)

Package

00000000h

558h

4

Input Stream Descriptor x DMA Position in Buffer Resume (OSD0DPIBR)

Package

00000000h

560h

4

Input Stream Descriptor x DMA Position in Buffer Resume (OSD1DPIBR)

Package

00000000h

568h

4

Input Stream Descriptor x DMA Position in Buffer Resume (OSD2DPIBR)

Package

00000000h

570h

4

Input Stream Descriptor x DMA Position in Buffer Resume (OSD3DPIBR)

Package

00000000h

578h

4

Input Stream Descriptor x DMA Position in Buffer Resume (OSD4DPIBR)

Package

00000000h

580h

4

Input Stream Descriptor x DMA Position in Buffer Resume (OSD5DPIBR)

Package

00000000h

588h

4

Input Stream Descriptor x DMA Position in Buffer Resume (OSD6DPIBR)

Package

00000000h

590h

4

Input Stream Descriptor x DMA Position in Buffer Resume (OSD7DPIBR)

Package

00000000h

598h

4

Input Stream Descriptor x DMA Position in Buffer Resume (OSD8DPIBR)

Package

00000000h

700h

4

Software Position Based FIFO Capability Header (SPBFCH)

Package

00040800h

704h

4

Software Position Based FIFO Control (SPBFCTL)

Package

00000000h

708h

4

Input / Output Stream Descriptor x Software Position in Buffer (ISD0SPIB)

Package

00000000h

70ch

4

Input / Output Stream Descriptor x Max FIFO Size (ISD0MAXFIFOS)

Package

00000000h

710h

4

Input / Output Stream Descriptor x Software Position in Buffer (ISD1SPIB)

Package

00000000h

714h

4

Input / Output Stream Descriptor x Max FIFO Size (ISD1MAXFIFOS)

Package

00000000h

718h

4

Input / Output Stream Descriptor x Software Position in Buffer (ISD2SPIB)

Package

00000000h

71ch

4

Input / Output Stream Descriptor x Max FIFO Size (ISD2MAXFIFOS)

Package

00000000h

720h

4

Input / Output Stream Descriptor x Software Position in Buffer (ISD3SPIB)

Package

00000000h

724h

4

Input / Output Stream Descriptor x Max FIFO Size (ISD3MAXFIFOS)

Package

00000000h

728h

4

Input / Output Stream Descriptor x Software Position in Buffer (ISD4SPIB)

Package

00000000h

72ch

4

Input / Output Stream Descriptor x Max FIFO Size (ISD4MAXFIFOS)

Package

00000000h

730h

4

Input / Output Stream Descriptor x Software Position in Buffer (ISD5SPIB)

Package

00000000h

734h

4

Input / Output Stream Descriptor x Max FIFO Size (ISD5MAXFIFOS)

Package

00000000h

738h

4

Input / Output Stream Descriptor x Software Position in Buffer (ISD6SPIB)

Package

00000000h

73ch

4

Input / Output Stream Descriptor x Max FIFO Size (ISD6MAXFIFOS)

Package

00000000h

740h

4

Input / Output Stream Descriptor x Software Position in Buffer (ISD7SPIB)

Package

00000000h

744h

4

Input / Output Stream Descriptor x Max FIFO Size (ISD7MAXFIFOS)

Package

00000000h

748h

4

Input / Output Stream Descriptor x Software Position in Buffer (ISD8SPIB)

Package

00000000h

74ch

4

Input / Output Stream Descriptor x Max FIFO Size (ISD8MAXFIFOS)

Package

00000000h

750h

4

Input / Output Stream Descriptor x Software Position in Buffer (ISD9SPIB)

Package

00000000h

754h

4

Input / Output Stream Descriptor x Max FIFO Size (ISD9MAXFIFOS)

Package

00000000h

758h

4

Input / Output Stream Descriptor x Software Position in Buffer (OSD0SPIB)

Package

00000000h

75ch

4

Input / Output Stream Descriptor x Max FIFO Size (OSD0MAXFIFOS)

Package

00000000h

760h

4

Input / Output Stream Descriptor x Software Position in Buffer (OSD1SPIB)

Package

00000000h

764h

4

Input / Output Stream Descriptor x Max FIFO Size (OSD1MAXFIFOS)

Package

00000000h

768h

4

Input / Output Stream Descriptor x Software Position in Buffer (OSD2SPIB)

Package

00000000h

76ch

4

Input / Output Stream Descriptor x Max FIFO Size (OSD2MAXFIFOS)

Package

00000000h

770h

4

Input / Output Stream Descriptor x Software Position in Buffer (OSD3SPIB)

Package

00000000h

774h

4

Input / Output Stream Descriptor x Max FIFO Size (OSD3MAXFIFOS)

Package

00000000h

778h

4

Input / Output Stream Descriptor x Software Position in Buffer (OSD4SPIB)

Package

00000000h

77ch

4

Input / Output Stream Descriptor x Max FIFO Size (OSD4MAXFIFOS)

Package

00000000h

780h

4

Input / Output Stream Descriptor x Software Position in Buffer (OSD5SPIB)

Package

00000000h

784h

4

Input / Output Stream Descriptor x Max FIFO Size (OSD5MAXFIFOS)

Package

00000000h

788h

4

Input / Output Stream Descriptor x Software Position in Buffer (OSD6SPIB)

Package

00000000h

78ch

4

Input / Output Stream Descriptor x Max FIFO Size (OSD6MAXFIFOS)

Package

00000000h

790h

4

Input / Output Stream Descriptor x Software Position in Buffer (OSD7SPIB)

Package

00000000h

794h

4

Input / Output Stream Descriptor x Max FIFO Size (OSD7MAXFIFOS)

Package

00000000h

798h

4

Input / Output Stream Descriptor x Software Position in Buffer (OSD8SPIB)

Package

00000000h

79ch

4

Input / Output Stream Descriptor x Max FIFO Size (OSD8MAXFIFOS)

Package

00000000h

800h

4

Processing Pipe Capability Header (PPCH)

Package

00030000h

804h

4

Processing Pipe Control (PPCTL)

Package

00000000h

808h

4

Processing Pipe Status (PPSTS)

Package

00000000h

8b0h

4

Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC0LLPL)

Package

00000000h

8b4h

4

Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC0LLPU)

Package

00000000h

8b8h

4

Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC0LDPL)

Package

00000000h

8bch

4

Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC0LDPU)

Package

00000000h

8c0h

4

Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC1LLPL)

Package

00000000h

8c4h

4

Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC1LLPU)

Package

00000000h

8c8h

4

Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC1LDPL)

Package

00000000h

8cch

4

Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC1LDPU)

Package

00000000h

8d0h

4

Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC2LLPL)

Package

00000000h

8d4h

4

Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC2LLPU)

Package

00000000h

8d8h

4

Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC2LDPL)

Package

00000000h

8dch

4

Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC2LDPU)

Package

00000000h

8e0h

4

Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC3LLPL)

Package

00000000h

8e4h

4

Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC3LLPU)

Package

00000000h

8e8h

4

Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC3LDPL)

Package

00000000h

8ech

4

Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC3LDPU)

Package

00000000h

8f0h

4

Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC4LLPL)

Package

00000000h

8f4h

4

Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC4LLPU)

Package

00000000h

8f8h

4

Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC4LDPL)

Package

00000000h

8fch

4

Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC4LDPU)

Package

00000000h

900h

4

Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC5LLPL)

Package

00000000h

904h

4

Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC5LLPU)

Package

00000000h

908h

4

Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC5LDPL)

Package

00000000h

90ch

4

Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC5LDPU)

Package

00000000h

910h

4

Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC6LLPL)

Package

00000000h

914h

4

Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC6LLPU)

Package

00000000h

918h

4

Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC6LDPL)

Package

00000000h

91ch

4

Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC6LDPU)

Package

00000000h

920h

4

Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC7LLPL)

Package

00000000h

924h

4

Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC7LLPU)

Package

00000000h

928h

4

Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC7LDPL)

Package

00000000h

92ch

4

Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC7LDPU)

Package

00000000h

930h

4

Input / Output Processing Pipes Host Connection on Linear Link Position Lower (OPPHC8LLPL)

Package

00000000h

934h

4

Input / Output Processing Pipes Host Connection on Linear Link Position Upper (OPPHC8LLPU)

Package

00000000h

938h

4

Input / Output Processing Pipes Host Connection on Linear DMA Position Lower (OPPHC8LDPL)

Package

00000000h

93ch

4

Input / Output Processing Pipes Host Connection on Linear DMA Position Upper (OPPHC8LDPU)

Package

00000000h

9e0h

4

Input / Output Processing Pipes Link Connection on Control (OPPLC0CTL)

Package

00000000h

9e4h

2

Input / Output Processing Pipes Link Connection on Format (OPPLC0FMT)

Package

0000h

9e8h

4

Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC0LLPL)

Package

00000000h

9ech

4

Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC0LLPU)

Package

00000000h

9f0h

4

Input / Output Processing Pipes Link Connection on Control (OPPLC1CTL)

Package

00000000h

9f4h

2

Input / Output Processing Pipes Link Connection on Format (OPPLC1FMT)

Package

0000h

9f8h

4

Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC1LLPL)

Package

00000000h

9fch

4

Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC1LLPU)

Package

00000000h

a00h

4

Input / Output Processing Pipes Link Connection on Control (OPPLC2CTL)

Package

00000000h

a04h

2

Input / Output Processing Pipes Link Connection on Format (OPPLC2FMT)

Package

0000h

a08h

4

Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC2LLPL)

Package

00000000h

a0ch

4

Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC2LLPU)

Package

00000000h

a10h

4

Input / Output Processing Pipes Link Connection on Control (OPPLC3CTL)

Package

00000000h

a14h

2

Input / Output Processing Pipes Link Connection on Format (OPPLC3FMT)

Package

0000h

a18h

4

Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC3LLPL)

Package

00000000h

a1ch

4

Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC3LLPU)

Package

00000000h

a20h

4

Input / Output Processing Pipes Link Connection on Control (OPPLC4CTL)

Package

00000000h

a24h

2

Input / Output Processing Pipes Link Connection on Format (OPPLC4FMT)

Package

0000h

a28h

4

Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC4LLPL)

Package

00000000h

a2ch

4

Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC4LLPU)

Package

00000000h

a30h

4

Input / Output Processing Pipes Link Connection on Control (OPPLC5CTL)

Package

00000000h

a34h

2

Input / Output Processing Pipes Link Connection on Format (OPPLC5FMT)

Package

0000h

a38h

4

Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC5LLPL)

Package

00000000h

a3ch

4

Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC5LLPU)

Package

00000000h

a40h

4

Input / Output Processing Pipes Link Connection on Control (OPPLC6CTL)

Package

00000000h

a44h

2

Input / Output Processing Pipes Link Connection on Format (OPPLC6FMT)

Package

0000h

a48h

4

Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC6LLPL)

Package

00000000h

a4ch

4

Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC6LLPU)

Package

00000000h

a50h

4

Input / Output Processing Pipes Link Connection on Control (OPPLC7CTL)

Package

00000000h

a54h

2

Input / Output Processing Pipes Link Connection on Format (OPPLC7FMT)

Package

0000h

a58h

4

Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC7LLPL)

Package

00000000h

a5ch

4

Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC7LLPU)

Package

00000000h

a60h

4

Input / Output Processing Pipes Link Connection on Control (OPPLC8CTL)

Package

00000000h

a64h

2

Input / Output Processing Pipes Link Connection on Format (OPPLC8FMT)

Package

0000h

a68h

4

Input / Output Processing Pipes Link Connection on Linear Link Position Lower (OPPLC8LLPL)

Package

00000000h

a6ch

4

Input / Output Processing Pipes Link Connection on Linear Link Position Upper (OPPLC8LLPU)

Package

00000000h

c00h

4

Multiple Links Capability Header (MLCH)

Package

00020500h

c04h

4

Multiple Links Capability Declaration (MLCD)

Package

00000001h

c40h

4

Link x Capabilities (LCAP0)

Package

00000007h

c44h

4

Link x Control (LCTL0)

Package

00010002h

c4ch

2

Link x SDI IDentifiers (LSDIID0)

Package

0007h

c50h

1

Link x Per Stream Output Overhead (LPSOO0)

Package

00h

c52h

1

Link x Per Stream Input Overhead (LPSIO0)

Package

02h

c58h

4

Link x Wall Frame Counter (LWALFC0)

Package

00000000h

c60h

2

Link x 6 MHz Output Payload Capability (LOUTPAY60)

Package

000Dh

c62h

2

Link x 12 MHz Output Payload Capability (LOUTPAY120)

Package

001Ch

c64h

2

Link x 24 MHz Output Payload Capability (LOUTPAY240)

Package

003Ch

c66h

2

Link x 48 MHz Output Payload Capability (LOUTPAY480)

Package

0000h

c68h

2

Link x 96 MHz Output Payload Capability (LOUTPAY960)

Package

0000h

c6ah

2

Link x 192 MHz Output Payload Capability (LOUTPAY1920)

Package

0000h

c70h

2

Link x 6 MHz Input Payload Capability (LINPAY60)

Package

0005h

c72h

2

Link x 12 MHz Input Payload Capability (LINPAY120)

Package

000Dh

c74h

2

Link x 24 MHz Input Payload Capability (LINPAY240)

Package

001Dh

c76h

2

Link x 48 MHz Input Payload Capability (LINPAY480)

Package

0000h

c78h

2

Link x 96 MHz Input Payload Capability (LINPAY960)

Package

0000h

c7ah

2

Link x 192 MHz Input Payload Capability (LINPAY1920)

Package

0000h

c80h

4

Link x Capabilities (LCAP1)

Package

00000007h

c84h

4

Link x Control (LCTL1)

Package

00010004h

c8ch

2

Link x SDI IDentifiers (LSDIID1)

Package

0007h

c90h

1

Link x Per Stream Output Overhead (LPSOO1)

Package

00h

c92h

1

Link x Per Stream Input Overhead (LPSIO1)

Package

02h

c98h

4

Link x Wall Frame Counter (LWALFC1)

Package

00000000h

ca0h

2

Link x 6 MHz Output Payload Capability (LOUTPAY61)

Package

000Dh

ca2h

2

Link x 12 MHz Output Payload Capability (LOUTPAY121)

Package

001Ch

ca4h

2

Link x 24 MHz Output Payload Capability (LOUTPAY241)

Package

003Ch

ca6h

2

Link x 48 MHz Output Payload Capability (LOUTPAY481)

Package

0000h

ca8h

2

Link x 96 MHz Output Payload Capability (LOUTPAY961)

Package

0000h

caah

2

Link x 192 MHz Output Payload Capability (LOUTPAY1921)

Package

0000h

cb0h

2

Link x 6 MHz Input Payload Capability (LINPAY61)

Package

0005h

cb2h

2

Link x 12 MHz Input Payload Capability (LINPAY121)

Package

000Dh

cb4h

2

Link x 24 MHz Input Payload Capability (LINPAY241)

Package

001Dh

cb6h

2

Link x 48 MHz Input Payload Capability (LINPAY481)

Package

0000h

cb8h

2

Link x 96 MHz Input Payload Capability (LINPAY961)

Package

0000h

cbah

2

Link x 192 MHz Input Payload Capability (LINPAY1921)

Package

0000h

1084h

4

Input / Output Stream Descriptor x DMA Position in Buffer (ISD0DPIB)

Package

00000000h

10a4h

4

Input / Output Stream Descriptor x DMA Position in Buffer (ISD1DPIB)

Package

00000000h

10c4h

4

Input / Output Stream Descriptor x DMA Position in Buffer (ISD2DPIB)

Package

00000000h

10e4h

4

Input / Output Stream Descriptor x DMA Position in Buffer (ISD3DPIB)

Package

00000000h

1104h

4

Input / Output Stream Descriptor x DMA Position in Buffer (ISD4DPIB)

Package

00000000h

1124h

4

Input / Output Stream Descriptor x DMA Position in Buffer (ISD5DPIB)

Package

00000000h

1144h

4

Input / Output Stream Descriptor x DMA Position in Buffer (ISD6DPIB)

Package

00000000h

1164h

4

Input / Output Stream Descriptor x DMA Position in Buffer (ISD7DPIB)

Package

00000000h

1184h

4

Input / Output Stream Descriptor x DMA Position in Buffer (ISD8DPIB)

Package

00000000h

11a4h

4

Input / Output Stream Descriptor x DMA Position in Buffer (ISD9DPIB)

Package

00000000h

11c4h

4

Input / Output Stream Descriptor x DMA Position in Buffer (OSD0DPIB)

Package

00000000h

11e4h

4

Input / Output Stream Descriptor x DMA Position in Buffer (OSD1DPIB)

Package

00000000h

1224h

4

Input / Output Stream Descriptor x DMA Position in Buffer (OSD3DPIB)

Package

00000000h

1c2ch

1

Latency Tolerance Reporting Policy (LTRP)

Package

80h

1c60h

4

Input Stream Repeat Count (INRC)

Package

00000000h

1d4ah

1

D0i3 Control (D0I3C)

Package

08h

1e28h

4

Power Transition Delay Control (PTDC)

Package

00104004h

1e30h

4

Function Configuration (FNCFG)

Package

0000002Ah

2030h

4

Wall Clock Counter Alias (WALCLKA)

Package

00000000h

2084h

4

Input/Output Stream Descriptor x Link Position in Buffer (ISD0LPIBA)

Package

00000000h

20a4h

4

Input/Output Stream Descriptor x Link Position in Buffer (ISD1LPIBA)

Package

00000000h

20c4h

4

Input/Output Stream Descriptor x Link Position in Buffer (ISD2LPIBA)

Package

00000000h

20e4h

4

Input/Output Stream Descriptor x Link Position in Buffer (ISD3LPIBA)

Package

00000000h

2104h

4

Input/Output Stream Descriptor x Link Position in Buffer (ISD4LPIBA)

Package

00000000h

2124h

4

Input/Output Stream Descriptor x Link Position in Buffer (ISD5LPIBA)

Package

00000000h

2144h

4

Input/Output Stream Descriptor x Link Position in Buffer (ISD6LPIBA)

Package

00000000h

2164h

4

Input/Output Stream Descriptor x Link Position in Buffer (ISD7LPIBA)

Package

00000000h

2184h

4

Input/Output Stream Descriptor x Link Position in Buffer (ISD8LPIBA)

Package

00000000h

21a4h

4

Input/Output Stream Descriptor x Link Position in Buffer (ISD9LPIBA)

Package

00000000h

21c4h

4

Input/Output Stream Descriptor x Link Position in Buffer (OSD0LPIBA)

Package

00000000h

21e4h

4

Input/Output Stream Descriptor x Link Position in Buffer (OSD1LPIBA)

Package

00000000h

2204h

4

Input/Output Stream Descriptor x Link Position in Buffer (OSD2LPIBA)

Package

00000000h

2224h

4

Input/Output Stream Descriptor x Link Position in Buffer (OSD3LPIBA)

Package

00000000h

2244h

4

Input/Output Stream Descriptor x Link Position in Buffer (OSD4LPIBA)

Package

00000000h

2264h

4

Input/Output Stream Descriptor x Link Position in Buffer (OSD5LPIBA)

Package

00000000h

2284h

4

Input/Output Stream Descriptor x Link Position in Buffer (OSD6LPIBA)

Package

00000000h

22a4h

4

Input/Output Stream Descriptor x Link Position in Buffer (OSD7LPIBA)

Package

00000000h

22c4h

4

Input/Output Stream Descriptor x Link Position in Buffer (OSD8LPIBA)

Package

00000000h