Interrupt Control (INTCTL) – Offset 20 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Interrupt Control (INTCTL) – Offset 20

The Interrupt Control register provides a central point for controlling interrupt generation. The SIE (Stream Interrupt Enable) register controls the interrupt mask for each individual Input or Output Stream. Setting a 1 in the appropriate bit allows the particular interrupt source to generate a processor interrupt. The CIE (Controller Interrupt Enable) controls the general controller interrupt. General controller interrupt sources are to a Response Interrupt, a Response Buffer Overrun, and State Change events. The GIE (Global Interrupt Enable) controls all hardware interrupt sources in the Intel HD Audio controller. If GIE is a 1, a processor interrupt may be requested- if GIE is a 0, then no processor interrupt may be requested.

Bit Range	Default	Access	Field Name and Description
31	0h	RW	Global Interrupt Enable (GIE) Global bit to enable device interrupt generation. When set to 1 the Intel HD Audio function is enabled to generate an interrupt. This control is in addition to any bits in the bus specific address space, such as the Interrupt Enable bit in the PCI Configuration Space.
30	0h	RW	Controller Interrupt Enable (CIE) Enables the general interrupt for controller functions. When set to 1 (and GIE is enabled), the controller generates an interrupt when the CIS bit gets set.
29:19	0h	RO	Reserved (RSVD2) This is a Reserved Register
18:0	0h	RW/L	Stream Interrupt Enable (SIE) When set to 1 the individual Streams are enabled to generate an interrupt when the corresponding stream status bits get set.A stream interrupt will be caused as a result of a buffer with IOC=1 in the BDL entry being completed, or as a result of a FIFO error (underrun or overrun) occurring. Control over the generation of each of these sources is in the associated Stream Descriptor.The streams are numbered and the SIE bits assigned sequentially, based on their order in the register set.