Interrupt Enable (IER) – Offset 4 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Interrupt Enable (IER) – Offset 4

Interrupt Enable Register. IER mode is only available when LCR register [7] (DLAB bit) = 0.

Bit Range	Default	Access	Field Name and Description
31:8	0h	NA	Res_31_8 (Res_31_8) Reserved
7	0h	RW	THRE Interrupt Mode Enable (PTIME) THRE Interrupt Mode Enable: This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled
6:5	0h	NA	Res_6_5 (Res_6_5) Reserved
4	0h	RW	Interrupt Enable Register (ELCOLR) Interrupt Enable Register: ELCOLR, this bit controls the method for clearing the status in the LSR register. This is applicable only for Overrun Error, Parity Error, Framing Error, and Break Interrupt status bits. 0 = LSR status bits are cleared either on reading Rx FIFO (RBR Read) or On reading LSR register. 1 = LSR status bits are cleared only on reading LSR register. Writeable only when LSR_STATUS_CLEAR == Enabled, always readable. Values: 0x0 (DISABLED): Disable ALC 0x1 (ENABLED): Enable ALC Value After Reset: 0x0
3	0h	RW	Enable Modem Status Interrupt (EDSSI) Enable Modem Status Interrupt: This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled
2	0h	RW	Enable Receiver Line Status Interrupt (ELSI) Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled
1	0h	RW	Enable Transmit Holding Register Empty Interrupt (ETBEI) Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled
0	0h	RW	Enable Received Data Available Interrupt (ERBFI) Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled