Interrupt Mask (IC_INTR_MASK) – Offset 30 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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xDCI PCI Configuration

Interrupt Mask (IC_INTR_MASK) – Offset 30

These bits mask their corresponding interrupt status bits in the IC_INTR_STAT register

Bit Range	Default	Access	Field Name and Description
31:15	0h	RO	Reserved (RSVD_IC_INTR_STAT)
14	0h	RO	Reserved (RSVD_M_SCL_STUCK_AT_LOW)
13	0h	RW	M_MASTER_ON_HOLD (M_MASTER_ON_HOLD) This bit masks the R_MST_ON_HOLD interrupt bit in the IC_INTR_STAT register.
12	0h	RO	M_RESTART_DET_read_only (M_RESTART_DET_read_only) This bit is RO.
11	1h	RW	M_GEN_CALL (M_GEN_CALL) This bit masks the R_GEN_CALL interrupt bit in the IC_INTR_STAT register.
10	0h	RW	M_START_DET (M_START_DET) This bit masks the R_START_DET interrupt bit in the IC_INTR_STAT register.
9	0h	RW	M_STOP_DET (M_STOP_DET) This bit masks the R_STOP_DET interrupt bit in the IC_INTR_STAT register.
8	0h	RW	M_ACTIVITY (M_ACTIVITY) This bit masks the R_ACTIVITY interrupt bit in the IC_INTR_STAT register.
7	0h	RO	Reserved
6	1h	RW	M_TX_ABRT (M_TX_ABRT) This bit masks the R_TX_ABRT interrupt bit in the IC_INTR_STAT register.
5	0h	RO	Reserved
4	1h	RW	M_TX_EMPTY (M_TX_EMPTY) This bit masks the R_TX_EMPTY interrupt bit in the IC_INTR_STAT register.
3	1h	RW	M_TX_OVER (M_TX_OVER) This bit masks the R_TX_OVER interrupt bit in the IC_INTR_STAT register.
2	1h	RW	M_RX_FULL (M_RX_FULL) This bit masks the R_RX_FULL interrupt bit in the IC_INTR_STAT register.
1	1h	RW	M_RX_OVER (M_RX_OVER) This bit masks the R_RX_OVER interrupt bit in the IC_INTR_STAT register.
0	1h	RW	M_RX_UNDER (M_RX_UNDER) This bit masks the R_RX_UNDER interrupt bit in the IC_INTR_STAT register.

Raw Interrupt Status (IC_RAW_INTR_STAT)

Interrupt Status (IC_INTR_STAT) Raw Interrupt Status (IC_RAW_INTR_STAT)