Interrupt Status (IC_INTR_STAT) – Offset 2c - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Interrupt Status (IC_INTR_STAT) – Offset 2c

Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register

Bit Range	Default	Access	Field Name and Description
31:14	0h	RO	Reserved
13	0h	RO	R_MASTER_ON_HOLD (R_MASTER_ON_HOLD) Indicates whether a master is holding the bus and the TX FIFO is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE = 1 and IC_EMPTYFIFO_HOLD_MASTER_EN = 1
12	0h	RO	Reserved
11	0h	RO	R_GEN_CALL (R_GEN_CALL) Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling the controller or when the processor reads bit 0 of the IC_CLR_GEN_CALL register
10	0h	RO	R_START_DET (R_START_DET) Indicates whether a START or RESTART condition has occurred on the I2C interface.
9	0h	RO	R_STOP_DET (R_STOP_DET) Indicates whether a STOP condition has occurred on the I2C interface.
8	0h	RO	R_ACTIVITY (R_ACTIVITY) This bit captures the controller activity and stays set until it is cleared. There are four ways to clear it: 1. Disabling the controller, 2. Reading the IC_CLR_ACTIVITY register, 3. Reading the IC_CLR_INTR register, 4. System reset Note: Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller is idle, this bit remains set until cleared, indicating that there was activity on the bus.
7	0h	RO	Reserved
6	0h	RO	R_TX_ABRT (R_TX_ABRT) This bit indicates if the controler, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes.
5:4	0h	RO	Reserved
3	0h	RO	R_TX_OVER (R_TX_OVER) Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
2	0h	RO	R_RX_FULL (R_RX_FULL) Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.
1	0h	RO	R_RX_OVER (R_RX_OVER) Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master goes into idle, and when ic_en goes to 0, this interrupt is cleared.
0	0h	RO	R_RX_UNDER (R_RX_UNDER) Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.