Interrupt Status (INTSTS) – Offset 24 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Interrupt Status (INTSTS) – Offset 24

The Interrupt Status register provides a central point for monitoring interrupt generation. The SIS (Stream Interrupt Status) indicates the current interrupt status of each interrupt source. A 1 indicates that an interrupt is being requested. Note that the state of these bits is independent of the SIE bits- even if the corresponding bit is set to a 0 in the Stream Interrupt Enable register to disable processor interrupt generation, the Status bit may still be set to indicate that stream is requesting service. This can be used by polling software to determine which Streams need attention without incurring system interrupts.The CIS (Controller Interrupt Status) indicates the status of the general controller interrupt. General controller interrupt sources are to a Response Interrupt, a Response Buffer Overrun, and State Change events. Note that the CIS is independent of the CIE bit- even if the CIE bit is set to a 0 to disable processor interrupt generation, the CIS bit may still be set to indicate that stream is requesting service.The GIS (Global Interrupt Status) indicates the status of all hardware interrupt sources in the Intel HD Audio controller. If GIS bit is a 1, a processor interrupt is currently being requested. Note that the GIS is independent of the GIE bit- even if the GIE bit is set to a 0 to disable processor interrupt generation, the GIS bit may still be set to indicate that stream is requesting service.

Bit Range	Default	Access	Field Name and Description
31	0h	RO/V	Global Interrupt Status (GIS) This bit is an OR of D0i3 interrupt, and all of the interrupt status bits in this register and PPSTS register.
30	0h	RW/V	Controller Interrupt Status (CIS) Status of general controller interrupt. A 1 indicates that an interrupt condition occurred due to a Response Interrupt, a Response Buffer Overrun Interrupt, CORB Memory Error Interrupt, or a SDIN State Change event. The exact cause can be determined by interrogating other registers. Note that a HW interrupt will not be generated unless the corresponding enable bit is set. This bit is an OR of all of the stated interrupt status bits for this register.
29:19	0h	RO	Reserved (RSVD5) This is a Reserved Register
18:0	0h	RW/V	Stream Interrupt Status (SIS) A 1 indicates that an interrupt condition occurred on the corresponding Stream. Note that a HW interrupt will not be generated unless the corresponding enable bit is set. This bit is an OR of all of an individual streams interrupt status bits.The streams are numbered and the SIS bits assigned sequentially, based on their order in the register set.