L1 Sub-States Capabilities (L1SCAP) – Offset 204 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

L1 Sub-States Capabilities (L1SCAP) – Offset 204

This is the L1 Sub-States Capabilities registers. Refer description for each individual field below for more details of the register functionality.

Bit Range	Default	Access	Field Name and Description
31:24	0h	RO	Reserved (RSVD_M) Reserved.
23:19	5h	RW/O	Port Tpower_on Value (PTV) Along with the Port Tpower_on Scale field in the L1 Substates Capabilities register sets the time(in us) that this Port requires the port on the opposite side of Link to wait in L1.OFF_EXIT after sampling CLKREQ asserted before actively driving the interface. Port Tpower_on is calculated by multiplying the value in this field by the value in the Port Tpower_on scale field in the L1 Sub-States Capabilities register. Required for all Ports that support L1.OFF.
18	0h	RO	Reserved
17:16	0h	RW/O	Port Tpower_on Scale (PTPOS) Specifies the scale used for Tpower_on value field in the L1 Substates Capabilities register. 00b: 2 us 01b: 10 us 10b: 100 us 11b: Reserved Required for all Ports that support L1.OFF.
15:8	28h	RW/O	Port Common Mode Restore Time (PCMRT) This is the time (in us) required for this Port to re-establish common mode. Required for all ports that support L1.OFF.
7	0h	RO	Reserved
6	0h	RW/1C/V	CLKREQ Acceleration Interrupt Status (L1SSEIS) For a Downstream Port that has both the CLKREQ Acceleration Supported and CLKREQ Acceleration Interrupt Enable bits Set, when set this bit indicates that the Port has completed the CLKREQ Acceleration Link Activation process, and that the Link has reached L0. Software must then clear this bit by writing a 1b to this bit. Must be hardwired to 0b for Upstream Ports. Default value is 0b.
5	0h	RW/O	CLKREQ Acceleration Supported (L1SSES) When set this bit indicates that this Port supports CLKREQ Accelration
4	1h	RW/O	L1 PM Substates Supported (L1PSS) When Set this bit indicates that this Port supports L1 PM Substates. For compatibility with possible future extensions, software must not enable L1 PM Substates unless this bit is set. This RWO field must be programmed prior to enabling ASPM. Required for both Upstream and Downstream Ports.
3	1h	RW/O	ASPM L1.1 Supported (AL11S) When set, this bit indicates ASPM L1.SNOOZ is supported. Required for both Upstream and Downstream ports. This RWO field must be programmed prior to enabling ASPM. Register Attribute: Static
2	1h	RW/O	ASPM L1.2 Supported (AL12S) When set, this bit indicates that ASPM L1.OFF is supported. Required for both Upstream and Downstream ports. This RWO field must be programmed prior to enabling ASPM. Register Attribute: Static
1	1h	RW/O	PCI-PM L1.1 Supported (PPL11S) When set, this bit indicates that PCI-PM L1.SNOOZ is supported and this bit must be set by all ports implementing L1 Sub-States. A port that supports L1.OFF must support L1.SNOOZ. Required for both upstream and downstream ports. This RWO field must be programmed prior to enabling ASPM. Register Attribute: Static
0	1h	RW/O	PCI-PM L1.2 Supported (PPL12S) When set, this bit indicates that PCI-PM L1.OFF is supported. Required for both upstream and downstream ports. This RWO field must be programmed prior to enabling ASPM. Register Attribute: Static.