Lane 2 And Lane 3 Equalization Control (L23EC) – Offset a40 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Lane 2 And Lane 3 Equalization Control (L23EC) – Offset a40

This is the Lane 2 And Lane 3 Equalization Control registers. Refer description for each individual field below for more details of the register functionality.

Bit Range	Default	Access	Field Name and Description
31	0h	RO	Reserved (RSVD_M) Reserved.
30:28	7h	RW	Upstream Port Lane 3 Receiver Preset Hint (UPL3RPH) Field contains the Receiver Preset Hint value sent or received during Port 8 GT/s Link Equalization.. \| \| Port Direction \| Crosslink Supported \| Usage \|A \| Downstream Port \| Any \| Contains value sent on the associated Lane during Link EQ. Register Attribute: Static.
27:24	fh	RW	Upstream Port Lane 3 Transmitter Preset Hint (UPL3TP) Field contains the Transmit Preset value sent or received during Port 8 GT/s Link Equalization. \| \| Port Direction \| Crosslink Supported \| Usage \|A \| Downstream Port \| Any \| Contains value sent on the associated Lane during Link EQ. Register Attribute: Static.
23	0h	RO	Reserved
22:20	7h	RW	Downstream Port Lane 3 Receiver Preset Hint (DPL3RPH) Receiver Preset Hint may be used as a hint for 8 GT/s receiver equalization by this Port when the Port is operating as a Downstream Port. Register Attribute: Static.
19:16	fh	RW	Downstream Port Lane 3 Transmitter Preset (DPL3TP) Transmitter Preset used for 8 GT/s equalization by this Port when the Port is operating as a Downstream Port. This field is ignored when the Port is operating as an Upstream Port. Register Attribute: Static.
15	0h	RO	Reserved
14:12	7h	RW	Upstream Port Lane 2 Receiver Preset Hint (UPL2RPH) Field contains the Receiver Preset Hint value sent or received during Port 8 GT/s Link Equalization.. \| \| Port Direction \| Crosslink Supported \| Usage \|A \| Downstream Port \| Any \| Contains value sent on the associated Lane during Link EQ. Register Attribute: Static.
11:8	fh	RW	Upstream Port Lane 2 Transmitter Preset (UPL2TP) Field contains the Transmit Preset value sent or received during Port 8 GT/s Link Equalization. \| \| Port Direction \| Crosslink Supported \| Usage \|A \| Downstream Port \| Any \| Contains value sent on the associated Lane during Link EQ. Register Attribute: Static.
7	0h	RO	Reserved
6:4	7h	RW	Downstream Port Lane 2 Receiver Preset Hint (DPL2RPH) Receiver Preset Hint may be used as a hint for 8 GT/s receiver equalization by this Port when the Port is operating as a Downstream Port. Register Attribute: Static.
3:0	fh	RW	Downstream Port Lane 2 Transmitter Preset (DPL2TP) Transmitter Preset used for 8 GT/s equalization by this Port when the Port is operating as a Downstream Port. This field is ignored when the Port is operating as an Upstream Port. Register Attribute: Static.