Lane 4 And Lane 5 Equalization Control (L45EC) – Offset a44 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Lane 4 And Lane 5 Equalization Control (L45EC) – Offset a44

This is the Lane 4 And Lane 5 Equalization Control registers. Refer description for each individual field below for more details of the register functionality.

Bit Range	Default	Access	Field Name and Description
31	0h	RO	Reserved (RSVD_M) Reserved.
30:28	0h	RO	Upstream Port Lane 5 Receiver Preset Hint (UPL5RPH) Field contains the Receiver Preset Hint value sent or received during Port 8 GT/s Link Equalization.. \| \| Port Direction \| Crosslink Supported \| Usage \|A \| Downstream Port \| Any \| Contains value sent on the associated Lane during Link EQ. Register Attribute: Static.
27:24	0h	RO	Upstream Port Lane 5 Transmitter Preset (UPL5TP) Field contains the Transmit Preset value sent or received during Port 8 GT/s Link Equalization. \| \| Port Direction \| Crosslink Supported \| Usage \|A \| Downstream Port \| Any \| Contains value sent on the associated Lane during Link EQ. Register Attribute: Static.
23	0h	RO	Reserved
22:20	0h	RO	Downstream Port Lane 5 Receiver Preset Hint (DPL5RPH) Receiver Preset Hint may be used as a hint for 8 GT/s receiver equalization by this Port when the Port is operating as a Downstream Port. Register Attribute: Static.
19:16	0h	RO	Downstream Port Lane 5 Transmitter Preset (DPL5TP) Transmitter Preset used for 8 GT/s equalization by this Port when the Port is operating as a Downstream Port. This field is ignored when the Port is operating as an Upstream Port. Register Attribute: Static.
15	0h	RO	Reserved
14:12	0h	RO	Upstream Port Lane 4 Receiver Preset Hint (UPL4RPH) Field contains the Receiver Preset Hint value sent or received during Port 8 GT/s Link Equalization.. \| \| Port Direction \| Crosslink Supported \| Usage \|A \| Downstream Port \| Any \| Contains value sent on the associated Lane during Link EQ. Register Attribute: Static.
11:8	0h	RO	Upstream Port Lane 4 Transmitter Preset (UPL4TP) Field contains the Transmit Preset value sent or received during Port 8 GT/s Link Equalization. \| \| Port Direction \| Crosslink Supported \| Usage \|A \| Downstream Port \| Any \| Contains value sent on the associated Lane during Link EQ. Register Attribute: Static.
7	0h	RO	Reserved
6:4	0h	RO	Downstream Port Lane 4 Receiver Preset Hint (DPL4RPH) Receiver Preset Hint may be used as a hint for 8 GT/s receiver equalization by this Port when the Port is operating as a Downstream Port. Register Attribute: Static.
3:0	0h	RO	Downstream Port Lane 4 Transmitter Preset (DPL4TP) Transmitter Preset used for 8 GT/s equalization by this Port when the Port is operating as a Downstream Port. This field is ignored when the Port is operating as an Upstream Port. Register Attribute: Static.