Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2
ID | Date | Version | Classification |
---|---|---|---|
834576 | 10/10/2024 | 001 | Public |
LFPS On Count (LFPSONCOUNT_REG) – Offset 81b8
LFPS On Count
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:23 | 0h | RW | Rsvd (RSVD) Reserved |
22 | 0h | RW | EN LFPS RX CONSOLIDATION (EN_LFPS_RX_CONSOLIDATION) When set, port will start comprehending LFPS on either of lane for the Resume Exits |
21 | 0h | RW | RTC Clock Generation Override (RTCCLKGENOVERRIDE) when set it will Disable the RTC tick generation unconditionally.This will be used by software to disable the tick and CRO if WDE/WCE is disabled |
20 | 0h | RO | Reserved |
19 | 0h | RW | Rx LFPS Filter 8us Enable (RXLFPSFILT_8US_EN) 0- RXLFPS detection filter for U3 Exit is 4 ticks of 128ns |
18 | 1h | RW | Disable RTC Polling (XDISRTCPOLLING) 1: Disable the RTC tick generation which is consumed for the RxDet Polling, LFPS Polling and Aux Clock PCG Wakup to enable this. |
17:16 | 0h | RW | U2P3 LFPS Periodic Sampling Control (XU2P3LPSC) This field controls the OFF time for the LFPS periodic sampling for SS and SSIC ports in U2P3. |
15:10 | 8h | RW | X LFPS On Count SSIC (XLFPSONCNTSSIC) This time would describe the number of clocks SSIC LFPS will remain ON. SSIC LFPS detection operation may be carried out on using RTC clock or Oscillator clock. The value of this register should be adjusted accordingly. |
9:0 | c8h | RW | X LFPS On Count SS (XLFPSONCNTSS) This time would describe the number of clocks LFPS will remain ON. LFPS detection operation may be carried out on using RTC clock or Oscillator clock. The value of this register should be adjusted accordingly. |