Link Error for eSPI First Device (LNKERR_SLV0) – Offset 4050 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Link Error for eSPI First Device (LNKERR_SLV0) – Offset 4050

This register is used to control link error reporting for the second eSPI device.

Bit Range	Default	Access	Field Name and Description
31	0h	RW/1C/V	eSPI Link and Device Channel Recovery Required (SLCRR) HW sets this bit when it has detected a Type 1 Fatal Error condition, for any channel (LFET1C is non-zero). Setting of this bit will trigger an error handling sequence by the eSPI controller, followed by the suspension of all HW initiated transactions on the eSPI link with the device. SW must clear this bit (by writing a 1 to it) after it has taken all necessary actions to recover the link. This indicates the eSPI-MC to resume HW initiated transactions with the device.
30:23	0h	RO	Reserved (RSVD) Reserved
22:21	0h	RW	Fatal Error Type 1 Reporting Enable (LFET1E) 2'b00: Disable Fatal Error Type 1 Reporting 2'b01: Reserved 2'b10: Enable Fatal Error Type 1 Reporting as SERR (IOSF-SB Do_SErr message) 2'b11: Enable Fatal Error Type 1 Reporting as SMI (IOSF-SB Assert_SMI message) SERR enable is also qualified by PCCMD.SEE (Offset 04h) when PLTRST# is deasserted. SERR also sets PCSTS.SSE (Offset 06h) when PLTRST# is deasserted. SMI/SERR messages are not generated if the Host is in reset (PLTRST# asserted). When this error is reported, SW must also inspect and handle the SLCRR field.
20	0h	RW/1C/V	Fatal Error Type 1 Reporting Status (LFET1S) This field is set by hardware if a Link Fatal Error Type 1 condition is detected on the eSPI link (any transaction). Software must clear this bit by writing a 1 to it. 1'b0: No Link Fatal Error Type 1 detected 1'b1: Fatal Error Type 1 detected (LFET1C has a non-zero value) Clearing this unlocks the LFET1C field and triggers an IOSF-SB Deassert_SMI message if LFET1E is set to SMI. Setting of this bit is independent of the enable to generate a SMI/SERR (LFET1E).
19:16	0h	RO/V	Link Fatal Type 1 cause (LFET1C) 4'h0: No error 4'h1: Device Response Code: NO_RESPONSE [Type 1] 4'h2: Device Response Code: FATAL_ERROR [Type 1] or length in header >= 512 Bytes 4'h3: Device Response Code: CRC_ERROR [Type 1] 4'h4: Invalid Device Response Code (w.r.t. to Command) [Type 1] 4'h5: Invalid Device Cycle Type (w.r.t. to Command) [Type 1] 4'h6 - 4'hF: Reserved This field is updated after a transaction (any channel) is completed if the LFET1S bit is clear. A non-zero value in this field also causes the SLCRR bit to be set.
15:8	ffh	RO/V	Link Fatal Error Type 1 Cycle Type (LFET1CTYP) When LFET1C is set, this field reflects the Cycle Type for the transaction that encountered the Fatal Error Type 1. If no valid Cycle Type exists w.r.t. the Command (LFET1CMD), this field is set to 8hFF to indicate that it should be ignored. This field is updated after a transaction (any channel) is completed if the LFET1S bit is clear.
7:0	0h	RO/V	Link Fatal Error Type 1 Command (LFET1CMD) When LFET1C is set, this field reflects the Command for the transaction that encountered the Fatal Error Type 1. This field is updated after a transaction (any channel) is completed if the LFET1S bit is clear.