Linked List Pointer High 0 (LLP_HI0) – Offset 814 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
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UART DMA
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xDCI MMIO Device
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xDCI PCI Configuration

Linked List Pointer High 0 (LLP_HI0) – Offset 814

This register needs to be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the channel if block chaining is enabled. This register must be programmed prior to enabling the channel in order to set up the transfer type. LLP.LOC != 0 contains the pointer to the next LLI for block chaining using linked lists. The LLPx register can also point to the address where write-back of the control and source/destination status information occur after block completion.

Bit Range	Default	Access	Field Name and Description
31:0	0h	RW	LOC (LOC) Starting Address In Memory of next LLI if block chaining is enabled. Note that the two LSBs of the starting address are not stored because the address is assumed to be aligned to a 32-bit boundary. LLI accesses are always 32-bit accesses and cannot be changed or programmed to anything other than 32-bit.

Bit Range

Default

Access

Field Name and Description

31:0

LOC (LOC)

Starting Address In Memory of next LLI if block chaining is enabled. Note that the
two LSBs of the starting address are not stored because the address is assumed to be
aligned to a 32-bit boundary. LLI accesses are always 32-bit accesses and cannot be
changed or programmed to anything other than 32-bit.

Control Register Low 0 (CTL_LO0)

Linked List Pointer Low 0 (LLP_LO0) Control Register Low 0 (CTL_LO0)