MSI Message Control (MMC) – Offset 62 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

MSI Message Control (MMC) – Offset 62

This register provides system software control over MSI.

Bit Range	Default	Access	Field Name and Description
15:11	0h	RO	Reserved (RSVD0) This is a Reserved Register
10	0h	RO	Extended Message Data Enable (EMDE) Not implemented
9	0h	RO	Extended Message Data Capable (EMDC) Not implemented
8	0h	RO	Per-Vector Masking Capable (PVMC) If Set, the Function supports MSI Per-Vector Masking. If Clear, the Function does not support MSI Per-Vector Masking.Not implemented.
7	1h	RO	64b Address Capability (ADD64) Indicates the ability to generate a 64-bit message address.
6:4	0h	RO	Multiple Message Enable (MME) Normally this is a RW register. However since only 1 message is supported, these bits are hardwired to 000 = 1 message.
3:1	0h	RO	Multiple Message Capable (MMC) Hardwired to 0 indicating request for 1 message.
0	0h	RW	MSI Enable (ME) If set to 1 an MSI will be generated instead of an INTx# signal. If set to 0, an MSI may not be generated.

MSI Message Lower Address (MMLA)

MSI Identifiers (MID) MSI Message Lower Address (MMLA)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

MSI Message Control (MMC) – Offset 62