MSI Message Control, Next Pointer And Capability ID (IDE_HOST_MSIMC_MSINP_MSICID) – Offset 40 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

MSI Message Control, Next Pointer And Capability ID (IDE_HOST_MSIMC_MSINP_MSICID) – Offset 40

This register contains the MSI message control, next pointer And capability ID values.

Bit Range	Default	Access	Field Name and Description
31:25	0h	RO	Reserved (RSVD)
24	0h	RO	Per Vector Masking Capable (PVMC) Not implemented. Hardwired to 0 to indicate the function does NOT support MSI per-vector masking.
23	1h	RO	64 Bit Address Capable (XAC) Hardwired to 1 to indicate the function is capable of sending a 64-bit message address.
22:20	0h	RW	Multiple Message Enable (MMEN) Encoded number of interrupt vectors allocated by SW. This field is RW for software compatibility, but only one interrupt vector is ever sent by the function.
19:17	0h	RO	Multiple Message Capable (MMC) Encoded number of interrupt vectors requested by a device. Hardwired to 0 to indicate one requested interrupt vector.
16	0h	RW	MSI Enable (MSIE) If set, MSI interrupt delivery is enabled whereas pin-based interrupt delivery SHALL be disabled. If cleared, prior to returning the configuration write (that clears this field) completion, the function must send any pending MSI(s).
15:8	50h	RO	Next Item Pointer (NP) Indicates the pointer for the next entry in the capabilities list. Hardwired to 50h to point to the PM Capability list
7:0	5h	RO	Capability ID (CID) Hardwired to 05h to indicate the linked list item as the MSI Capability registers

MSI Message Address (IDE_HOST_MSIMA)

Maximum Latency, Minimum Grant, Interrupt Pin And Interrupt Line (IDE_HOST_MAXL_MING_INTP_INTL) MSI Message Address (IDE_HOST_MSIMA)

Select Your Language

Using Intel.com Search

Quick Links

Recent Searches

Advanced Search

Only search in

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

MSI Message Control, Next Pointer And Capability ID (IDE_HOST_MSIMC_MSINP_MSICID) – Offset 40