Output Stream Descriptor x FIFO Size (OSD0FIFOS) – Offset 1d0 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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Output Stream Descriptor x FIFO Size (OSD0FIFOS) – Offset 1d0

This register reports the FIFO size of the output stream DMA.

Bit Range	Default	Access	Field Name and Description
15:0	0h	RW/V	FIFO Size (FIFOS) Indicates the maximum number of bytes that could be fetched by the controller at one time. This is the maximum number of bytes that may have been received into the HW buffer but not yet transferred out, and is also the maximum possible value that the PICB count will increase by at one time.The FIFO size is calculated based on the stream format programmed in OSDxFMT register, the min frame of buffering setting in EM4.OSBSMFA[1:0] field, and the minimum buffer size threshold setting in EM2.BSMT[1:0] field. As the default value is zero, SW must write to the OSDxFMT register to kick off the FIFO size calculation, and read back to find out the HW allocated FIFO size.

Bit Range

Default

Access

Field Name and Description

15:0

RW/V

FIFO Size (FIFOS)

Indicates the maximum number of bytes that could be fetched by the controller at one time. This is the maximum number of bytes that may have been received into the HW buffer but not yet transferred out, and is also the maximum possible value that the PICB count will increase by at one time.The FIFO size is calculated based on the stream format programmed in OSDxFMT register, the min frame of buffering setting in EM4.OSBSMFA[1:0] field, and the minimum buffer size threshold setting in EM2.BSMT[1:0] field. As the default value is zero, SW must write to the OSDxFMT register to kick off the FIFO size calculation, and read back to find out the HW allocated FIFO size.

Output Stream Descriptor x Format (OSD0FMT)

Output Stream Descriptor x FIFO Eviction Watermark (OSD0FIFOW) Output Stream Descriptor x Format (OSD0FMT)