Output Stream Descriptor x Status (OSD0STS) – Offset 1c3 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Output Stream Descriptor x Status (OSD0STS) – Offset 1c3

This register provides the status of the output stream DMA.

Bit Range	Default	Access	Field Name and Description
7:6	0h	RO	Reserved (RSVD1) This is a Reserved Register
5	0h	RO/V	FIFO Ready (FIFORDY) This bit defaults to 0 on reset because the FIFO is cleared on a reset. For output streams, the controller hardware will set this bit to a 1 while the output DMA FIFO contains enough data to maintain the stream on then link.
4	0h	RW/1C/V	Descriptor Error (DESE) Indicates that a serious error occurred during the fetch of a descriptor. This could be a result of a Master Abort, a Parity or ECC error on the bus, or any other error which renders the current Buffer Descriptor or Buffer Descriptor List useless. This error is treated as a fatal stream error, as the stream cannot continue running. The RUN bit will be cleared and the stream will stop. Software may attempt to restart the stream engine after addressing the cause of the error and writing a 1 to this bit to clear it.
3	0h	RW/1C/V	FIFO Error (FIFOE) Set when a FIFO error occurs. Bit is cleared by writing a 1 to this bit position. This bit is set even if an interrupt is not enabled.Input Stream:For an input stream, this indicates a FIFO overrun occurring while the RUN bit is set. When this happens, the FIFO pointers dont increment and the incoming data is not written into the FIFO, thereby being lost.Output Stream:For an output stream, this indicates a FIFO under run when there are still buffers to send. The hardware should not transmit anything on the link for the associated stream if there is not valid data to send.
2	0h	RW/1C/V	Buffer Completion Interrupt Status (BCIS) This bit is set to 1 by the hardware after the last sample of a buffer has been processed, AND if the Interrupt on Completion (IOC) bit is set in the command byte of the buffer descriptor. It remains active until software clears it by writing a 1 to this bit position.
1:0	0h	RO	Reserved (RSVD2) This is a Reserved Register