Over-Clocking WDT Control (OC_WDT_CTL) – Offset 54 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Over-Clocking WDT Control (OC_WDT_CTL) – Offset 54

This register controls the operation of the Over-Clocking Watchdog Timer.

Bit Range	Default	Access	Field Name and Description
31	0h	WO	Over-Clocking WDT Reload (OC_WDT_RLD) Software can write a '1' to this bit to reload the PCH over-clocking watchdog timer while it is running. A write of '0' to this bit has no effect. A write of '1' to this bit while OC_WDT_EN=0, or with the clearing of OC_WDT_EN, does not start or reload the WDT (i.e. OC_WDT_EN takes precedence). The value in OC_WDT_TOV may be changed by software along with its setting of this bit. On a WDT reload, the current (potentially new) value in OC_WDT_TOV is loaded into the WDT as the new timeout value.
30:26	0h	RO	Reserved (RSVD30_26) Reserved
25	0h	RW/1C/V	Over-Clocking WDT ICC Survivability Mode Timeout Status (OC_WDT_ICCSURV_STS) This bit is set to '1' if the over-clocking WDT has timed out and triggered a global reset while running in a mode that has ICC survivability impact (OC_WDT_ICCSURV=1). It is cleared by a software write of '1' or by the RSMRST# pin.
24	0h	RW/1C/V	Over-Clocking WDT Non-ICC Survivability Mode Timeout Status (OC_WDT_NO_ICCSURV_STS) This bit is set to '1' if the over-clocking WDT has timed out and triggered a global reset while running in a mode that does not have ICC survivability impact (OC_WDT_ICCSURV=0). It is cleared by a software write of '1' or by the RSMRST# pin.
23:16	0h	RW	Over-Clocking WDT Scratchpad (OC_WDT_SCRATCH) This field is available as scratchpad space for software and has no effect on PCH HW operation.
15	0h	RW/L	Over-Clocking WDT Force All (OC_WDT_FORCE_ALL) GATE_BIT:OC_WDT_CTL.OC_WDT_CTL_LCK.HIGH When this bit is set to 1 and the OC_WDT is running, any included global reset source will behave as though the OC_WDT expired.
14	0h	RW/V/L	Over-Clocking WDT Enable (OC_WDT_EN) Software sets this bit to '1' to enable the PCH over-clocking watchdog timer. While the counter is running, if it expires before being reloaded by software via the OC_WDT_RLD bit or halted by software clearing this bit, then one of the status bits will be set (which one depends on the WDT operating mode at the time - see the OC_WDT_ICCSURV bit description), and a global reset will be triggered. This bit is also set by the hardware when conditions allow the OC_WDT to self-start at power cycle reboot (effectively changes the default of this bit as seen by software).
13	1h	RW/L	Over-Clocking WDT ICC Survivability Impact (OC_WDT_ICCSURV) This bit determines whether OC_WDT expiration will have an impact on ICC (Integrated Clock Controller) bootstrap survivability. OC_WDT_ICCSURV=1 (default) An OC_WDT timeout while operating in this mode causes certain ICC hardware auto-recovery actions to take place. Refer to ICC C-spec chapter 38 for more details. A timeout in this mode will set OC_WDT_ICCSURV_STS. OC_WDT_ICCSURV=0 Software should configure the OC_WDT to this mode if no ICC hardware auto-recovery actions are desired in the event of a timeout. A timeout in this mode will set OC_WDT_NO_ICCSURV_STS.
12	0h	RW/L	OC_WDT_CTL Register Lock (OC_WDT_CTL_LCK) This bit controls write-ability to this register. Encodings: 0: All fields of register OC_WDT_CTL operate as normal and can be updated by software. Reads to the register operate as normal. 1: All RW/L fields of register OC_WDT_CTL, including this lock control bit, are locked. Writes to these register fields have no effect and the register fields retain their current states. Reads to the register operate as normal. Once this bit is set, it can only be cleared by CORE well power loss.
11:10	0h	RO	Reserved (RSVD11_10) Reserved
9:0	0h	RW/V/L	Over-Clocking WDT Timeout Value (OC_WDT_TOV) Software programs the desired over-clocking WDT timeout value into this register. This timer is zero-based and has a granularity of 1 second. Example timeout values: 000h: 1 second 001h: 2 seconds ... 3FFh: ~17 minutes (1024 seconds) The value of OC_WDT_TOV may be changed by software along with its setting of the OC_WDT_RLD bit. On a WDT reload, the current (potentially new) value in OC_WDT_TOV is loaded into the WDT as the new timeout value. This field is also updated by the hardware when conditions allow the OC_WDT to self-start at power cycle reboot (effectively changes the default of this field as seen by software).