Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_8) – Offset 870 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Pad Configuration DW0 (PAD_CFG_DW0_GPP_K_8) – Offset 870

Bit Range	Default	Access	Field Name and Description
31:30	1h	RW	Pad Reset Config (PADRSTCFG) Same description as PADRSTCFG bit in PAD_CFG_DW0_GPP_K_0 register.
29	0h	RW	RX Pad State Select (RXPADSTSEL) Same description as RXPADSTSEL bit in PAD_CFG_DW0_GPP_K_0 register.
28	0h	RW	RX Raw Override to '1' (RXRAW1) Same description as RXRAW1 bit in PAD_CFG_DW0_GPP_K_0 register.
27	0h	RO	Native Function Virtual Wire Message Enable (NAF_VWE) Same description as NAF_VWE bit in PAD_CFG_DW0_GPP_K_0 register.
26:25	2h	RW	RX Level/Edge Configuration (RXEVCFG) Same description as RXEVCFG bit in PAD_CFG_DW0_GPP_K_0 register.
24	0h	RW	Pre Glitch Filter Stage RX Pad State Select (PREGFRXSEL) Same description as PREGFRXSEL bit in PAD_CFG_DW0_GPP_K_0 register.
23	0h	RW	RX Invert (RXINV) Same description as RXINV bit in PAD_CFG_DW0_GPP_K_0 register.
22:21	0h	RO	RX/TX Enable Config (RXTXENCFG) Same description as RXTXENCFG bit in PAD_CFG_DW0_GPP_K_0 register.
20	0h	RW	GPIO Input Route IOxAPIC (GPIROUTIOXAPIC) Same description as GPIROUTIOXAPIC bit in PAD_CFG_DW0_GPP_K_0 register.
19	0h	RW	GPIO Input Route SCI (GPIROUTSCI) Same description as GPIROUTSCI bit in PAD_CFG_DW0_GPP_K_0 register.
18	0h	RO	GPIO Input Route SMI (GPIROUTSMI) Same description as GPIROUTSMI bit in PAD_CFG_DW0_GPP_K_0 register.
17	0h	RO	GPIO Input Route NMI (GPIROUTNMI) Same description as GPIROUTNMI bit in PAD_CFG_DW0_GPP_K_0 register.
16:13	0h	RO	Reserved (RSVD_0) Reserved
12:10	1h	RW	Pad Mode (PMODE) Same description as PMODE bit in PAD_CFG_DW0_GPP_K_0 register.
9	1h	RW	GPIO RX Disable (GPIORXDIS) Same description as GPIORXDIS bit in PAD_CFG_DW0_GPP_K_0 register.
8	1h	RW	GPIO TX Disable (GPIOTXDIS) Same description as GPIOTXDIS bit in PAD_CFG_DW0_GPP_K_0 register.
7:2	0h	RO	Reserved (RSVD_1) Reserved
1		RO/V	GPIO RX State (GPIORXSTATE) Same description as GPIORXSTATE bit in PAD_CFG_DW0_GPP_K_0 register.
0	0h	RW	GPIO TX State (GPIOTXSTATE) Same description as GPIOTXSTATE bit in PAD_CFG_DW0_GPP_K_0 register.