Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2
ID | Date | Version | Classification |
---|---|---|---|
834576 | 10/10/2024 | 001 | Public |
Pad Configuration Lock (PADCFGLOCK_DSW_0) – Offset 110
Refer to Register Field for detail
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:17 | 0h | RO | Reserved (RSVD_0) Reserved |
16:13 | 0h | RO | Reserved |
12 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPD_12) Same description as bit 0. |
11 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPD_11) Same description as bit 0. |
10 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPD_10) Same description as bit 0. |
9 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPD_9) Same description as bit 0. |
8 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPD_8) Same description as bit 0. |
7 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPD_7) Same description as bit 0. |
6 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPD_6) Same description as bit 0. |
5 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPD_5) Same description as bit 0. |
4 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPD_4) Same description as bit 0. |
3 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPD_3) Same description as bit 0. |
2 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPD_2) Same description as bit 0. |
1 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPD_1) Same description as bit 0. |
0 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPD_0) PadCfgLock locks specific register fields in the pad specific registers (in Community or Pad) from being configured. The registers affected become Read-Only and software writes to these registers have no effect. |