Pad Configuration Lock (PADCFGLOCK_GPP_A_0) – Offset 110 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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xDCI PCI Configuration

Pad Configuration Lock (PADCFGLOCK_GPP_A_0) – Offset 110

Refer to Register Field for detail

Bit Range	Default	Access	Field Name and Description
31:15	0h	RO	Reserved (RSVD_0) Reserved
14	0h	RO	Reserved
13	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_A_13) Same description as bit 0.
12	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_A_12) Same description as bit 0.
11	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_A_11) Same description as bit 0.
10	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_A_10) Same description as bit 0.
9	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_A_9) Same description as bit 0.
8	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_A_8) Same description as bit 0.
7	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_A_7) Same description as bit 0.
6	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_A_6) Same description as bit 0.
5	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_A_5) Same description as bit 0.
4	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_A_4) Same description as bit 0.
3	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_A_3) Same description as bit 0.
2	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_A_2) Same description as bit 0.
1	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_A_1) Same description as bit 0.
0	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_A_0) PadCfgLock locks specific register fields in the pad specific registers (in Community or Pad) from being configured. The registers affected become Read-Only and software writes to these registers have no effect. This field is meaningful and takes effect only if the pad is owned by host (refer to PAD_OWN register). Pads under other ownership are not affected by the PadCfgLock. 0 = Unlock 1 = Lock the following register fields as read-only (RO): - Pad Configuration registers (exclude GPIOTXState) - GPI_NMI_EN Register (if implemented) - HOSTSW_OWN Registers (if implemented)

Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_A_0)

Pad Ownership (PAD_OWN_GPP_B_2) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_A_0)