Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2
| ID | Date | Version | Classification |
|---|---|---|---|
| 834576 | 10/10/2024 | 001 | Public |
Pad Configuration Lock (PADCFGLOCK_GPP_E_0) – Offset 118
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:23 | 0h | RO | Reserved (RSVD_0) Reserved |
| 22 | 0h | RO | Reserved |
| 21 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_21) Same description as bit 0. |
| 20 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_20) Same description as bit 0. |
| 19 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_19) Same description as bit 0. |
| 18 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_18) Same description as bit 0. |
| 17 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_17) Same description as bit 0. |
| 16 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_16) Same description as bit 0. |
| 15 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_15) Same description as bit 0. |
| 14 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_14) Same description as bit 0. |
| 13 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_13) Same description as bit 0. |
| 12 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_12) Same description as bit 0. |
| 11 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_11) Same description as bit 0. |
| 10 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_10) Same description as bit 0. |
| 9 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_9) Same description as bit 0. |
| 8 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_8) Same description as bit 0. |
| 7 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_7) Same description as bit 0. |
| 6 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_6) Same description as bit 0. |
| 5 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_5) Same description as bit 0. |
| 4 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_4) Same description as bit 0. |
| 3 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_3) Same description as bit 0. |
| 2 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_2) Same description as bit 0. |
| 1 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_1) Same description as bit 0. |
| 0 | 0h | RW | Pad Config Lock (PADCFGLOCK_GPP_E_0) PadCfgLock locks specific register fields in the pad specific registers (in Community or Pad) from being configured. The registers affected become Read-Only and software writes to these registers have no effect. |