Pad Configuration Lock (PADCFGLOCK_GPP_S_0) – Offset 110 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
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- AHCI Index Register (INDEX)
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- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
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THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Pad Configuration Lock (PADCFGLOCK_GPP_S_0) – Offset 110

Bit Range	Default	Access	Field Name and Description
31:8	0h	RO	Reserved (RSVD_0) Reserved
7	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_S_7) Same description as bit 0.
6	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_S_6) Same description as bit 0.
5	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_S_5) Same description as bit 0.
4	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_S_4) Same description as bit 0.
3	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_S_3) Same description as bit 0.
2	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_S_2) Same description as bit 0.
1	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_S_1) Same description as bit 0.
0	0h	RW	Pad Config Lock (PADCFGLOCK_GPP_S_0) PadCfgLock locks specific register fields in the pad specific registers (in Community or Pad) from being configured. The registers affected become Read-Only and software writes to these registers have no effect. This field is meaningful and takes effect only if the pad is owned by host (refer to PAD_OWN register). Pads under other ownership are not affected by the PadCfgLock. 0 = Unlock 1 = Lock the following register fields as read-only (RO): - Pad Configuration registers (exclude GPIOTXState) - GPI_NMI_EN Register (if implemented) - HOSTSW_OWN Registers (if implemented)

Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_S_0)

Pad Ownership (PAD_OWN_GPP_F_2) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_S_0)