PCI Power Management Control and Status (THC_CFG_PMD_PMCSRBSE_PMCSR) – Offset 74 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
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I2C MMIO
I3C / I2C / UART / GSPI PCR
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I3C DMA
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I3C PCI Configuration
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Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
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Intel(R) Management Engine Interface (MEI) PCI Configuration
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Intel® High Definition Audio PCI Configuration
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- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
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- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
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SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
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SMBus PCI Configuration
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SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

PCI Power Management Control and Status (THC_CFG_PMD_PMCSRBSE_PMCSR) – Offset 74

Bit Range	Default	Access	Field Name and Description
31:16	0h	RO	Reserved (RSVD_31_16) Reserved.
15	0h	RW/1C/V	PME Status (PMESTS) See PCI Power Management Interface specification. This bit is set when the THC would normally assert the PME# signal independent of the state of the PME_En bit. Writing a 1 to this bit will clear it and cause the internal PME to deassert (if enabled). Writing a 0 has no effect. This bit must be explicitly cleared by the operating system each time the operating system is loaded.
14:13	0h	RO	Data Scale (DS) This is register is fro Data Scale
12:9	0h	RO	Data Select (DSEL) This register is for Data Select
8	0h	RW	PME Enable (PMEEN) See PCI Power Management Interface specification.
7:4	0h	RO	Reserved (RSVD_7_4) Reserved.
3	1h	RO	No Soft Reset (NSR) When set to 1, this bit indicates that devices transitioning from D3hot to D0 because of PowerState commands do not perform an internal reset. Configuration Context is preserved. Upon transition from the D3hot to the D0 Initialized state, no additional operating system intervention is required to preserve Configuration Context beyond writing the PowerState bits.
2	0h	RO	Reserved (RSVD_2) Reserved.
1:0	0h	RW/V	Power State (PWRST) This 2-bit field is used both to determine the current power state of THC function and to set a new power state. The definition of the field values are: 00b - D0 state 11b - D3hot state If software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally however, the data is discarded and no state change occurs. When in the D3hot state, the Intel PCH must not accept accesses to the THC memory range but the configuration space must still be accessible.

Device Idle Capability (THC_CFG_DEVIDLE)

PCI Power Management Capability (THC_CFG_PMCAP_PMNP_PMCID) Device Idle Capability (THC_CFG_DEVIDLE)