PCI Power Management Control (PMCS) – Offset a4 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

PCI Power Management Control (PMCS) – Offset a4

This is the PCI Power Management Control registers. Refer description for each individual field below for more details of the register functionality.

Bit Range	Default	Access	Field Name and Description
31:24	0h	RO	Data (DTA) Reserved.
23	0h	RO	Bus Power / Clock Control Enable (BPCE) Reserved per PCI Express specification
22	0h	RO	B2/B3 Support (B23S) Reserved per PCI Express specification.
21:16	0h	RO	Reserved
15	0h	RO	PME Status (PMES) Indicates a PME was received on the downstream link.
14:13	0h	RO	Data Scale (DSC) Reserved.
12:9	0h	RO	Data Select (DSEL) Reserved.
8	0h	RW/P	PME Enable (PMEE) Indicates PME is enabled. The root port takes no action on this bit, but it must be RW for legacy Microsoft operating systems to enable PME on devices connected to this root port.
7:4	0h	RO	Reserved
3	1h	RW/O	No Soft Reset (NSR) When set to 1 this bit indicates that devices transitioning from D3hot to D0 because of Power State commands do not perform an internal reset. Configuration context is preserved. Upon transition from D3hot to D0 Initialized state, no additional operating system intervention is required to preserve Configuration Context beyond writing the Power State bits. When clear, devices do perform an internal reset upon transitioning from D3hot to D0 via software control of the Power State bits. Configuration Context is lost when performing the soft reset. Upon transition from D3hot to D0 state, full reinitialization sequence is needed to return the device to D0 Initialized. Regardless of this bit, devices that transition from D3hot to D0 by a system or bus segment reset will return to the device state D0 Uninitialized with only PME context preserved if PME is supported and enabled.
2	0h	RO	Reserved
1:0	0h	RW	Power State (PS) This field is used both to determine the current power state of the root port and to set a new power state. The values are: 00: D0 state 11: D3HOT state When in the D3HOT state, the controllers configuration space is available, but the I/O and memory spaces are not. Type 1 configuration cycles are also not accepted. Interrupts are not required to be blocked as software will disable interrupts prior to placing the port into D3HOT. If software attempts to write a 10 or 01 to these bits, the write will be ignored.