Peripheral Channel Error for ESPI Device 0 (PCERR_SLV0) – Offset 4020 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Peripheral Channel Error for ESPI Device 0 (PCERR_SLV0) – Offset 4020

Bit Range	Default	Access	Field Name and Description
31:29	0h	RO	Reserved (RSVD) Reserved
28	0h	RW	Device Host Reset Ack Override (SLV_HOST_RST_ACK_OVRD) A 1 in this bit will cause the eSPI-MC to not wait for the Device HOST_RESET_ACK Virtual Wire before (immediately) asserting the ResetPrepAck (Host space, GenPrep). The Host_Reset_Warn VW will be transmitted to the device independent of the setting for this bit.
27:26	0h	RW	Peripheral Channel Received Master or Target Abort Reporting Enable (PCRMTARE) 2'b00: Disable RMA or RTA Reporting 2'b01: Reserved 2'b10: Enable RMA or RTA Reporting as SERR (IOSF-SB Do_SErr message) 2'b11: Enable RMA or RTA Reporting as SMI (IOSF-SB Assert_SMI message) SERR enable is also qualified by PCCMD.SEE (Offset 04h) when PLTRST# is deasserted. SERR also sets PCSTS.SSE (Offset 06h) when PLTRST# is deasserted.
25	0h	RW	Peripheral Channel Unsupported Request Reporting Enable (PCURRE) If set to 1 by software, it allows reporting of an Unsupported Request (UR) as a System Error (SERR). If eSPI-MC decodes a Posted transaction on IOSF-P Host Root Space that is not supported, it sets the PCURD bit. If PCCMD.SEE (SERR enable) is also set to 1, then eSPI-MC sets the PCSTS.SSE (Signaled System Error) bit and sends a Do_SErr message on its IOSF-SB interface. If the transaction was a Non-Posted request, then the agent handles the transaction as an Advisory Non-Fatal error, and no error logging or signaling is done. The Completion with UR Completion Status serves the purpose of error reporting.
24	0h	RW/1C/V	Peripheral Channel Unsupported Request Detected (PCURD) Set to 1 by hardware upon detecting an Unspported Request (UR) that is not considered an Advisory Non-Fatal error and PCERR.PCURRE is set. Cleared to 0 when software writes a 1 to this register.
23:15	0h	RO	Reserved 1 (RSVD1) Reserved
14:13	0h	RW	Peripheral Channel Non-Fatal Error Reporting Enable (PCNFEE) 2'b00: Disable Non-Fatal Error Reporting 2'b01: Reserved 2'b10: Enable Non-Fatal Error Reporting as SERR (IOSF-SB Do_SErr message) 2'b11: Enable Non-Fatal Error Reporting as SMI (IOSF-SB Assert_SMI message) SERR enable is also qualified by PCCMD.SEE (Offset 04h) when PLTRST# is deasserted. SERR also sets PCSTS.SSE (Offset 06h) when PLTRST# is deasserted. SMI/SERR messages are not generated if the Host is in reset (PLTRST# asserted).
12	0h	RW/1C/V	Peripheral Channel Non-Fatal Status (PCNFES) This field is set by hardware if a Non-Fatal Error condition is detected on the Peripheral Channel. Software must clear this bit. 1'b0: No Non-Fatal Error detected 1'b1: Non-Fatal Error detected (PCNFEC has a non-zero value) Clearing this unlocks the PCNFEC field and triggers an IOSF-SB Deassert_SMI message if PCNFEE is set to SMI. Setting of this bit is independent of the enable to generate a SMI/SERR (PCNFEE).
11:8	0h	RO/V	Peripheral Channel Non-Fatal Cause (PCNFEC) 4'h0: No error 4'h1: Device Response Code: NONFATAL_ERROR 4'h2: Device Response Code: Unsuccessful Completion 4'h3: Unexpected completion received from device (i.e. completion without non-posted request or completion with invalid tag or completion with invalid length) 4'h4: Unsupported Cycle Type (w.r.t. Command) 4'h5: Unsupported Message Code 4'h6: Unsupported Address/Length alignment (upstream only): Memory: Address + Length > 64 B (aligned) [for both Posted and Non-Posted transactions] 4'h7: Unsupported Address/Length alignment (upstream only): Memory: 64-bit Address with Addr[63:32] = 0h [for both Posted and Non-Posted transactions] 4'h8 - 4'hF: Reserved This field is updated after a Peripheral channel transaction is completed if the PCNFES bit is not set.
7	1h	RW	PLCC Misaligned Memory Access (PMMA) Applies to only posted and non-posted memory transactions directed towards D31:f0 to be sent over the eSPI Peripheral Channel to an eSPI device. 1'b0: Requests with a length of 3 bytes or requests with a length of 1/2/4 bytes whose Address+Length is not DWord aligned will be rejected. 1'b1: Requests with a length of 3 bytes or requests with a lenght of 1/2/4 butes whose Address+Length is not DWord aligned will be sent to the device using the memory write/read format.
6:5	0h	RW	Peripheral Channel Fatal Error Reporting (PCFEE) 2'b00: Disable Fatal Error Reporting 2'b01: Reserved 2'b10: Enable Fatal Error Reporting as SERR (IOSF-SB Do_SErr message) 2'b11: Enable Fatal Error Reporting as SMI (IOSF-SB Assert_SMI message) SERR enable is also qualified by PCCMD.SEE (Offset 04h) when PLTRST# is deasserted. SERR also sets PCSTS.SSE (Offset 06h) when PLTRST# is deasserted. SMI/SERR messages are not generated if the Host is in reset (PLTRST# asserted).
4	0h	RW/1C/V	Peripheral Channel Fatal Error Reporting (PCFES) This field is set by hardware if a Fatal Error condition is detected on the Peripheral Channel. Software must clear this bit by writing a 1 to it. 1'b0: No Fatal Error detected 1'b1: Fatal Error Type 2 detected (PCFEC has a non-zero value) Clearing this unlocks the PCFEC field and triggers an IOSF-SB Deassert_SMI message if PCFEE is set to SMI. Setting of this bit is independent of the enable to generate a SMI/SERR (PCFEE).
3:0	0h	RO/V	Peripheral Channel Fatal Error Cause (PCFEC) 4'h0: No error 4'h1 4'h7: Reserved 4'h8: Malformed Device Response Payload: Payload length > Max Payload Size (aligned) [Type 2] 4'h9: Malformed Device Response Payload: Read request size > Max Read Request Size (aligned) [Type 2] 4'hA: Malformed Device Response Payload: Address + Length > 4KB (aligned) [Type 2] 4'hB - 4'hF: Reserved This field is updated after a Peripheral channel transaction is completed if the PCFES bit is not set.