Port 1 Interrupt Status (PxIS1) – Offset 190 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Port 1 Interrupt Status (PxIS1) – Offset 190

Bit Range	Default	Access	Field Name and Description
31	0h	RO	Cold Presence Detect Status (CPDS) The SATA controller does not support cold presence detect.
30	0h	RW/1C/V	Task File Error Status (TFES) This bit is set whenever the status register is updated by the device and the error bit (bit 0 of the Status field in the received FIS) is set.
29	0h	RW/1C/V	Host Bus Fatal Error Status (HBFS) Indicates that the HBA encountered a host bus error that it cannot recover from, such as a bad software pointer. In PCI, such an indication would be a target or master abort.
28	0h	RW/1C/V	Host Bus Data Error Status (HBDS) Indicates that the HBA encountered a data error (uncorrectable ECC / parity) when reading from or writing to system memory.
27	0h	RW/1C/V	Interface Fatal Error Status (IFS) Indicates that the HBA encountered an error on the SATA interface which caused the transfer to stop.
26	0h	RW/1C/V	Interface Non-fatal Error Status (INFS) Indicates that the HBA encountered an error on the SATA interface but was able to continue operation.
25	0h	RO	RSVD0 (RSVD0) Reserved
24	0h	RW/1C/V	Overflow Status (OFS) Indicates that the HBA received more bytes from a device than was specified in the PRD table for the command.
23	0h	RW/1C/V	Incorrect Port Multiplier Status (IPMS) Indicates that the HBA received a FIS from a device whose port multiplier field did not match what was expected. The IPMS bit may be set during emuneration process. It is recommended that IPMS only be used after enumeration is complete on the Port Multiplier.Port Multiplier is not supported.
22	0h	RO/V	PhyRdy Change Status (PRCS) When set to one indicates the internal PhyRdy signal changed state. This bit reflects the state of PxSERR.DIAG.N. This bit is RO and is only cleared when PxSERR.DIAG.N is cleared. The internal PhyRdy signal also transitions when the port interface enters PARTIAL or SLUMBER power management states. PARTIAL and SLUMBER must be disabled when Surprise Removal Notification is desired, otherwise the power management state transitions will appear as false insertion and removal events.
21:8	0h	RO	RSVD1 (RSVD1) Reserved
7	0h	RW/1C/V	Device Mechanical Presence Status (DMPS) When set, indicates that a platform mechanical presence switch has been opened or closed, which may lead to a change in the connection state of the device. This bit is only valid in systems that support mechanical presence switch (CAP.SMPS and PxCMD.MPSP are set). For systems that do not support mechanical presence switch, this bit will always be 0.
6	0h	RO/V	Port Connect Change Status (PCS) 1=Change in Current Connect Status. 0=No change in Current Connect Status. This bit reflects the state of PxSERR.DIAG.X. This bit is only cleared when PxSERR.DIAG.X is cleared.
5	0h	RW/1C/V	Descriptor Processed (DPS) A PRD with the I bit set has transferred all of its data.
4	0h	RO/V	Unknown FIS Interrupt (UFS) When set to 1 indicates that an unknown FIS was received and has been copied into system memory. This bit is cleared to 0 by software clearing the PxSERR.DIAG.F bit to 0. Note that this bit does not directly reflect the PxSERR.DIAG.F bit. PxSERR.DIAG.F is set immediately when an unknown FIS is detected, whereas this bit is set when the FIS is posted to memory. Software should wait to act on an unknown FIS until this bit is set to 1 or the two bits may become out of sync.
3	0h	RW/1C/V	Set Device Bits Interrupt (SDBS) A Set Device Bits FIS has been received with the I bit set and has been copied into system memory.
2	0h	RW/1C/V	DMA Setup FIS Interrupt (DSS) A DMA Setup FIS has been received with the I bit set and has been copied into system memory.
1	0h	RW/1C/V	PIO Setup FIS Interrupt (PSS) A PIO Setup FIS has been received with the I bit set, it has been copied into system memory, and the data related to that FIS has been transferred. This bit shall be set even if the data transfer resulted in an error.
0	0h	RW/1C/V	Device to Host Register FIS Interrupt (DHRS) A D2H register FIS has been received with the I bit set, and has been copied into system memory.