Port 3 Command (PxCMD3) – Offset 298 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Port 3 Command (PxCMD3) – Offset 298

Bit Range	Default	Access	Field Name and Description
31:28	0h	RW	Interface Communication Control (ICC) This field is used to control power management states of the interface. If the Link layer is currently in the L_IDLE state, writes to this field shall cause the HBA to initiate a transition to the interface power management state requested. If the Link layer is not currently in the L_IDLE state, writes to this field shall have no effect. When system software writes a non-reserved value other than No-Op (0h), the HBA shall perform the action and update this field back to Idle (0h). If software writes to this field to change the state to a state the link is already in (i.e. interface is in the active state and a request is made to go to the active state), the HBA shall take no action and return this field to Idle. If the interface is in a low power state and the software wants to transition to a different low power state, software must first bring the link to active and then initiate the transition to the desired low power state (with the exception of DEVSLP). The transition to DEVSLP may occur from any other state if CAP2.DESO is cleared to 0. If CAP2.DESO is set to 1, then DEVSLP may only be transitioned to if the link is in Slumber.
27	0h	RW	Aggressive Slumber Partial (ASP) When set to 1, and the ALPE bit is set, the HBA shall aggressively enter the Slumber state when it clears a bit in the PxCI or PxSACT register and the register values are then PxCI = 0h and PxSACT = 0h. When cleared, and the ALPE bit is set, the HBA will aggressively enter the Partial state when it clears a bit in the PxCI or PxSACT register and the register values are then PxCI = 0h and PxSACT = 0h. If CAP.SALP is cleard to 0, software shall treat this bit as reserved.
26	0h	RW	Aggressive Link Power Management Enable (ALPE) When set, the HBA will aggressively enter a lower link power state (Partial or Slumber) based upon the setting of the ASP bit. Software shall only set this bit to 1 if CAP.SALP is set to 1. If CAP.SALP is cleared to 0, software shall treat this bit as reserved. BIOS is recommeded to program this field to 1.
25	0h	RW	Drive LED on ATAPI Enable (DLAE) When set, the HBA will drive the LED pin active for commands regardless of the state of PxCMD.ATAPI. When cleared, the HBA will only drive the LED pin active for commands if PxCMD.ATAPI is set to 0. This bit is set by software
24	0h	RW	Device is ATAPI (ATAPI) When set, the connected device is an ATAPI device. This bit is used by the HBA to control whether or not to generate the desktop LED when commands are active.
23	0h	RW	Automatic Partial to Slumber Transitions Enabled (APSTE) When set to 1, the HBA may perform Automatic Partial to Slumber Transitions. When cleared to 0 the port shall not perform Automatic Partial to Slumber Transitions. Software shall only set this bit to 1 if CAP2.APST is set to 1; if CAP2.APST is cleared to 0 software shall treat this bit as reserved.
22	0h	RO	FIS-based Switching Capable Port (FBSCP) The SATA controller does not support FIS-Based Switching.
21	0h	RW/O	External SATA Port (ESP) When set to 1, indicates that this port is routed externally and will be used with an external SATA device. When set to 1, CAP.SXS must also be set to 1. When cleared (0), indicates that this port is not routed externally and supports internal SATA devices only. If ESP is set to 1, then the port may experience hot plug events. Note : This bit is not reset on a HBA reset.
20	0h	RO	Cold Presence Detection (CPD) The SATA controller does not support cold presence detect.
19	0h	RW/O	Mechanical Presence Switch Attached to Port (MPSP) If set to 1, the platform supports a mechanical presence switch attached to this port. If cleared to 0, the platform does not support a mechanical presence switch attached to this port. When this bit is set to 1, PxCMD.HPCP should also be set to 1. The HBA takes no action on the state of this bit, it is for system software only. For example, if this bit is cleared, and an interlock switch toggles, the HBA shall still treat it as a proper interlock switch event. Note that this bit is not reset on a HBA reset.
18	0h	RW/O	Hot Plug Capable Port (HPCP) This indicates whether the this port is connected to a device which can be hot plugged. SATA by definition is hot-pluggable, but not all platforms are constructed to allow the device to be removed (it may be screwed into the chassis, for example). This bit can be used by system software to indicate a feature such as eject device to the end-user. The HBA takes no action on the state of this bit, it is for system software only. For example, if this bit is cleared, and a hot plug event occurs, the HBA shall still treat it as a proper hot plug event. This bit is not reset on a HBA reset.
17	0h	RW/V	Port Multiplier Attached (PMA) When set, a Port Multiplier is attached to the HBA for this port. When cleared, a Port Multiplier is not attached to the HBA for this port. This bit is a read only 0. when CAP.PMS = 0, and read/write when CAP.PMS = 1. Note that this bit is set by software; hardware does not auto-detect that a Port Multiplier is attached.
16	0h	RO	RSVD0 (RSVD0) Reserved
15	0h	RO/V	Command List Running (CR) When this bit is set it indicates that the command list DMA engine for the port is running.
14	0h	RO/V	FIS Receive Running (FR) When this bit is set it indicates that the FIS Receive DMA engine for the port is running. Note to software: When FR bit stays set, please read the PxIS.PCS and PxSERR.DET.X to service the PCS interrupt accordingly if any
13	0h	RO/V	Mechanical Presence Switch State (MPSS) The MPSS bit reports the state of a mechanical presence switch attached to this port. If CAP.SMPS is set to 1 and the mechanical presence switch is closed then this bit is cleared to 0. If CAP.SMPS is set to 1 and the mechanical presence switch is open then this bit is set to 1. If CAP.SMPS is set to 0 then this bit is cleared to 0. Software should only use this bit if both CAP.SMPS and PxCMD.MPSP are set to 1.
12:8	0h	RO/V	Current Command Slot (CCS) Indicates the current command slot the HBA is processing. This field is valid when the PxCMD.ST bit is set, and is constantly updated by the HBA. This field can be updated as soon as the HBA recognizes an active command slot, or at some point soon after when it begins processing the command. When PxCMD.ST transitions from a 1 to a 0, the HBA will reset this field to 0. After PxCMD.ST transitions from 0 to 1, the highest priority slot to issue from next is command slot 0. After the first command has been issued, the highest priority slot to issue from next is PxCMD.CCS + 1. For example, after the HBA has issued its first command, if PxCMD.CCS = 0h and PxCI is set to 3h, the next command that will be issued is from command slot 1.
7:5	0h	RO	RSVD1 (RSVD1) Reserved
4	0h	RW	FIS Receive Enable (FRE) When set, the HBA may post received FISes into the FIS receive area pointed to by PxFB and PxFBU. When cleared, received FISes are not accepted by the HBA, except for the first D2H register FIS after the initialization sequence. System software must not set this bit until PxFB and PxFBU have been programmed with a valid pointer to the FIS receive area. If software wishes to move the base, this bit must first be cleared, and software must wait for the PxCMD.FR bit to be cleared before updating PxFB and PxFBU. Software must not clear this bit while PxCMD.ST is set to 1.
3	0h	RW/1S/V	Command List Override (CLO) Setting this bit to 1 causes PxTFD.STS.BSY and PxTFD.STS.DRQ to be cleared to 0. This allows a software reset to be transmitted to the device regardless of whether the BSY and DRQ bits are still set in the PxTFD.STS register. The HBA sets this bit to 0 when PxTFD.STS.BSY and PxTFD.STS.DRQ have been cleared to 0. A write to this register with a value of 0 shall have no effect. This bit shall only be set to 1 immediately prior to setting the PxCMD.ST bit to 1 from a previous value of 0. Setting this bit to 1 at any other time is not supported and will result in indeterminate behavior. Software must wait for CLO to be cleard to 0 before setting PxCMD.ST to 1.
2	1h	RO	Power On Device (POD) The SATA controller does not support cold presence detect.
1	0h	RW/V	Spin-Up Device (SUD) This bit is read/write for HBAs that support staggered spin-up via CAP.SSS. This bit is read only 1 for HBAs that do not support staggered spin-up. On an edge detect from 0 to 1, the HBA shall start a COMRESET initializatoin sequence to the device. Clearing this bit causes no action on the interface. Clearing this bit to 0 does not cause any OOB signal to be sent on the interface. When this bit is cleared to 0 and PxSCTL.DET = 0h, the HBA will enter listen mode.
0	0h	RW	Start (ST) When set, the HBA may process the command list. When cleared, the HBA may not process the command list. Whenever this bit is changed from a 0 to a 1, the HBA starts processing the command list at entry 0. Whenever this bit is changed from a 1 to a 0, the PxCI and PxSACT register is cleared by the HBA upon the HBA putting the controller into an idle state. PxTFD shall be updated also. See section 10.3.1 of the AHCI spec for restrictions on when PxCMD.ST can be set to 1 and cleared to 0.