Port 3 Interrupt Enable (PxIE3) – Offset 294 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Port 3 Interrupt Enable (PxIE3) – Offset 294

This register enables and disables the reporting of the corresponding interrupt to system software. When a bit is set (1) and the corresponding interrupt condition is active, then an interrupt is generated. Interrupt sources that are disabled (0) are still reflected in the status registers. This register is symmetrical with the Port 0 Status register.

Bit Range	Default	Access	Field Name and Description
31	0h	RO	Cold Presence Detect Enable (CPDE) The SATA controller does not support cold presence detect.
30	0h	RW	Task File Error Enable (TFEE) When set, GHC.IE is set, and P0S.TFES is set, the HBA shall generate an interrupt.
29	0h	RW	Host Bus Fatal Error Enable (HBFE) When set, GHC.IE is set, and P0IS.HBFS is set, the HBA shall generate an interrupt.
28	0h	RW	Host Bus Data Error Enable (HBDE) when set, GHC.IE is set, and P0IS.HBDS is set, the HBA shall generate an interrupt.
27	0h	RW	Interface Fatal Error Enable (IFE) When set, GHC.IE is set, and P0IS.IFS is set, the HBA shall generate an interrupt.
26	0h	RW	Interface Non-fatal Error Enable (INFE) When set, GHC.IE is set, and P0IS.INFS is set, the HBA shall generate an interrupt.
25	0h	RO	RSVD0 (RSVD0) Reserved
24	0h	RW	Overflow Enable (OFE) When set, and GHC.IE and P0IS.OFS are set, the HBA shall generate an interrupt.
23	0h	RW	Incorrect Port Multiplier Enable (IPME) When set, and GHC.IE and P0IS.IPMS are set, the HBA shall generate an interrupt. BIOS is required to program this field to '0'. The same applies to AHCI driver.
22	0h	RW	PhyRdy Change Interrupt Enable (PRCE) When set, and GHC.IE is set, and PxIS.PRCS is set, the HBA shall generate an interrupt.
21:8	0h	RO	RSVD1 (RSVD1) Reserved
7	0h	RW/V	Device Mechanical Presence Enable (DMPE) When set, and P0IS.DMPS is set, the HBA shall generate an interrupt.
6	0h	RW	Port Change Interrupt Enable (PCE) When set, GHC.IE is set, and P0IS.PCS is set, the HBA shall generate an interrupt.
5	0h	RW	Descriptor Processed Interrupt Enable (DPE) When set, GHC.IE is set, and P0IS.DPS is set, the HBA shall generate an interrupt.
4	0h	RW	Unknown FIS Interrupt Enable (UFE) When set, GHC.IE is set, and PxIS.UFS is set to 1, the HBA shall generate an interrupt.
3	0h	RW	Set Device Bits FIS Interrupt Enable (SDBE) When set, GHC.IE is set, and P0IS.SDBS is set, the HBA shall generate an interrupt.
2	0h	RW	DMA Setup FIS Interrupt Enable (DSE) When set, GHC.IE is set, and P0IS.DSS is set, the HBA shall generate an interrupt.
1	0h	RW	PIO Setup FIS Interrupt Enable (PSE) When set, GHC.IE is set, and P0IS.PSS is set, the HBA shall generate an interrupt.
0	0h	RW	Device to Host Register FIS Interrupt Enable (DHRE) When set, GHC.IE is set, and P0IS.DHRS is set, the HBA shall generate an interrupt.