Port 5 Serial ATA Error (PxSERR5) – Offset 3b0 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Port 5 Serial ATA Error (PxSERR5) – Offset 3b0

Bit Range	Default	Access	Field Name and Description
31:27	0h	RW/1C/V	RSVD0 (RSVD0) Reserved
26	0h	RW/1C/V	Diagnostics Exchange (DIAG_X) Contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. Bit 26(Exchanged) : When set to one this bit indicates that a change in device presence has been detected since the last time this bit was cleared. The means by which the implementation determines that the device presence has changed is vendor specific. This bit shall always be set to one anytime a COMINIT signal is received. This bit is reflected in the P0IS.PCS bit.
25	0h	RW/1C/V	Diagnostics Unrecognized FIS Type (DIAG_F) Contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. Bit 25(Unrecognized FIS Type) : Indicates that one or more FISs were received by the Transport layer with good CRC, but had a type field that was not recognized/known.
24	0h	RW/1C/V	Diagnostics Transport State Transition error (DIAG_T) Contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. Bit 24(Transport state transition error) : Indicates that an error has occurred in the transition from one state to another within the Transport layer since the last time this bit was cleared.
23	0h	RW/1C/V	Diagnostics Link Sequence Error (DIAG_S) Contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. Bit 23(Link Sequence Error) : Indicates that one or more Link state machine error conditions were encountered. The Link Layer state machine defines the conditions under which the link layer detects an erroneous transition.
22	0h	RW/1C/V	Diagnostics Handshake Error (DIAG_H) Contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. Bit 22(Handshake Error) : Indicates that one or more R_ERR handshake response was received in response to frame transmission. Such errors may be the result of a CRC error detected by the recipient, a disparity or 8b/10b decoding error, or other error condition leading to a negative handshake on a transmitted frame.
21	0h	RW/1C/V	Diagnostics CRC Error (DIAG_C) Contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. Bit 21(CRC Error) : Indicates that one or more CRC errors occurred with the Link Layer.
20	0h	RW/1C/V	Diagnostics Disparity Error (DIAG_D) Contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. Bit 20(Disparity Error ) : This field is not used by AHCI. This bit is not implemented and always read only '0'.
19	0h	RW/1C/V	Diagnostics 10B to 8B Decode Error (DIAG_B) Contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. Bit 19(10B to 8B Decode Error) : Indicates that one or more 10B to 8B decoding errors occurred.
18	0h	RW/1C/V	Diagnostics Comm Wake (DIAG_W) Contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. Bit 18(Comm Wake) : Indicates that a Comm Wake signal was detected by the Phy.
17	0h	RW/1C/V	Diagnostics Phy Internal Error (DIAG_I) Contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. Bit 17(Phy Internal Error) : Indicates that the Phy detected some internal error. This bit is not implemented and always read only '0'.
16	0h	RW/1C/V	Diagnostics PhyRdy Change (DIAG_N) Contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. Bit 16(PhyRdy Change) : When set to 1 this bit indicates that the internal PhyRdy signal changed state since the last time this bit was cleared. The state of this bit is reflected in the PxIS.PRCS interrupt status bit and an interrupt will be generated if enabled.
15:12	0h	RW/1C/V	RSVD1 (RSVD1) Reserved
11	0h	RW/1C/V	Error Internal Error (ERR_E) The ERR field contains error information for use by host software in determining the appropriate response to the error condition. If one or more of bits 11:8 of this register are set, the controller will stop the current transfer. Bit 11(Internal Error) : The SATA controller failed due to a master or target abort when attempting to access system memory.
10	0h	RW/1C/V	Error Protocol Error (ERR_P) The ERR field contains error information for use by host software in determining the appropriate response to the error condition. If one or more of bits 11:8 of this register are set, the controller will stop the current transfer. Bit 10(Protocol Error) : A violation of the Serial ATA protocol was detected.
9	0h	RW/1C/V	Error Persistent Communication or Data Integrity Error (ERR_C) The ERR field contains error information for use by host software in determining the appropriate response to the error condition. If one or more of bits 11:8 of this register are set, the controller will stop the current transfer. Bit 9(Persistent Communication or Data Integrity Error): A communication error that was not recovered occurred that is expected to be persistent. Persistent communications errors may arise from faulty interconnect with the device, from a device that has been removed or has failed, or a number of other causes. This bit is not implemented and always read only '0'.
8	0h	RW/1C/V	Error Transient Data Integrity Error (ERR_T) The ERR field contains error information for use by host software in determining the appropriate response to the error condition. If one or more of bits 11:8 of this register are set, the controller will stop the current transfer. Bit 8(Transient Data Integrity Error) : A data integrity error occurred that was not recovered by the interface.
7:2	0h	RW/1C/V	RSVD2 (RSVD2) Reserved
1	0h	RW/1C/V	Error Recovered Communications Error (ERR_M) The ERR field contains error information for use by host software in determining the appropriate response to the error condition. If one or more of bits 11:8 of this register are set, the controller will stop the current transfer. Bit 1(Recovered Communications Error) : Communications between the device and host was temporarily lost but was re-established. This can arise from a device temporarily being removed, from a temporary loss of Phy synchronization, or from other causes and may be derived from the PhyNRdy signal between the Phy and Link layers.
0	0h	RW/1C/V	Error Recovered Data Integrity Error (ERR_I) The ERR field contains error information for use by host software in determining the appropriate response to the error condition. If one or more of bits 11:8 of this register are set, the controller will stop the current transfer. Bit 0(Recovered Data Integrity Error) : A data integrity error occurred that was recovered by the interface through a retry operation or other recovery action.