Port Control And Status (PCS) – Offset 94 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Port Control And Status (PCS) – Offset 94

By default, the SATA ports are set (by hardware) to the disabled state (e.g. bits[5:0] == '0') as a result of an initial power on reset. When enabled by software, the ports can transition between the on, partial, and slumber states and can detect devices. When disabled, the port is in the off state and cannot detect any devices. Note: This register is not reset by FLR. Note: AHCI specific notes: If an AHCI-aware or RAID enabled operating system is being booted then system BIOS shall insure that all supported SATA ports are enabled prior to passing control to the OS. Once the AHCI aware OS is booted it becomes the enabling/disabling policy owner for the individual SATA ports. This is accomplished by manipulating a port's PxSCTL.DET and PxCMD.SUD fields. Because an AHCI or RAID aware OS will typically not have knowledge of the PxE bits and because the PxE bits act as master on/off switches for the ports, pre-boot software must insure that these bits are set to '1' prior to booting the OS, regardless as to whether or not a device is currently on the port.

Bit Range	Default	Access	Field Name and Description
31:24	0h	RO	RSVD0 (RSVD0) Reserved
23	0h	RO/V	Port 7 Present (P7P) Same as P0P, except for port 7. This bit is only applicable to project(s) that has port 7 physically.
22	0h	RO/V	Port 6 Present (P6P) Same as P0P, except for port 6. This bit is only applicable to project(s) that has port 6 physically.
21	0h	RO/V	Port 5 Present (P5P) Same as P0P, except for port 5. This bit is only applicable to project(s) that has port 5 physically.
20	0h	RO/V	Port 4 Present (P4P) Same as P0P, except for port 4. This bit is only applicable to project(s) that has port 4 physically.
19	0h	RO/V	Port 3 Present (P3P) Same as P0P, except for port 3. This bit is only applicable to project(s) that has port 3 physically.
18	0h	RO/V	Port 2 Present (P2P) Same as P0P, except for port 2. This bit is only applicable to project(s) that has port 2 physically.
17	0h	RO/V	Port 1 Present (P1P) Same as P0P, except for port 1. This bit is only applicable to project(s) that has port 1 physically.
16	0h	RO/V	Port 0 Present (P0P) This bit is set when COMINIT is received as a response to COMRESET. When set, the SATA controller has detected the presence of a device on port 0. It may change at any time. Clearing P0E bit leads to clearing of this bit after implementation delay. Software that intends to clear all PCS.PxE bits that are previously 1 to 0 and then to 1 again in two consecutive write cycles, software shall poll on this bit being 0 before setting P0E bit to 1. This bit is only applicable to project(s) that has port 0 physically.
15:8	0h	RO	RSVD1 (RSVD1) Reserved
7	0h	RW/V	Port 7 Enabled (P7E) When MAP.SPD[7] is 1, this bit is reserved and is read-only 0. Otherwise this field is RW and the definition of this bit is same as P0E, except for port 7. This bit takes precedence over P7CMD.SUD. BIOS shall program the P7E to 1 prior to starting the AHCI initialization flow. This bit is only applicable to project(s) that has port 7 physically.
6	0h	RW/V	Port 6 Enabled (P6E) When MAP.SPD[6] is 1, this bit is reserved and is read-only 0. Otherwise this field is RW and the definition of this bit is the same as P0E, except for port 6. This bit takes precedence over P6CMD.SUD. BIOS shall program the P6E to 1 prior to starting the AHCI initialization flow. This bit is only applicable to project(s) that have port 6 physically.
5	0h	RW/V	Port 5 Enabled (P5E) When MAP.SPD[5] is 1, this bit is reserved and is read-only 0. Otherwise this field is RW and the definition of this bit is the same as P0E, except for port 5. This bit takes precedence over P5CMD.SUD. BIOS shall program the P5E to 1 prior to starting the AHCI initialization flow. This bit is only applicable to project(s) that has port 5 physically.
4	0h	RW/V	Port 4 Enabled (P4E) When MAP.SPD[4] is 1, this bit is reserved and is read-only 0. Otherwise this bit is RW and same as P0E but for port 4 and takes precedence over P4CMD.SUD. BIOS shall program the P4E to 1 prior to starting the AHCI initialization flow. This bit is only applicable to project(s) that has port 4 physically.
3	0h	RW/V	Port 3 Enabled (P3E) When MAP.SPD[3] is 1, this bit is reserved and is read-only 0. Otherwise this bit is RW and same as P0E but for port 3 and takes precedence over P3CMD.SUD. BIOS shall program the P3E to 1 prior to starting the AHCI initialization flow. This bit is only applicable to project(s) that has port 3 physically.
2	0h	RW/V	Port 2 Enabled (P2E) When MAP.SPD[2] is 1, this bit is reserved and is read-only 0. Otherwise this bit is RW and same as P0E but for port 2 and takes precedence over P2CMD.SUD. BIOS shall program the P2E to 1 prior to starting the AHCI initialization flow. This bit is only applicable to project(s) that has port 2 physically.
1	0h	RW/V	Port 1 Enabled (P1E) When MAP.SPD[1] is 1, this bit is reserved and read-only 0. Otherwise this bit is RW and same as P0E but for port 1 and takes precedence over P1CMD.SUD. BIOS shall program the P1E to 1 prior to starting the AHCI initialization flow. RO-zero condition: MAP.SPD[1] is 1, OR SATA PORT muxing for port 1 based on fuses, soft straps and GPIO does not select SATA, OR Fuse FFSATA8 (disable port 1 & 3) is 1. This bit is only applicable to project(s) that has port 1 physically.
0	0h	RW/V	Port 0 Enabled (P0E) When MAP.SPD[0] is 1, this bit is reserved and read-only 0. When set, the port is enabled. When cleared, the port is disabled. When enabled, the port can transition between the on, partial, and slumber states and can detect devices. When disabled, the port is in the off state and cannot detect any devices. This bit takes precedence over P0CMD.SUD. BIOS shall program the P0E to 1 prior to starting the AHCI initialization flow. The recommendation for software code that intends to clear all PCS.PxE bits that are previously 1 to 0 and then to 1 again immediately shall refer to the polling requirement as described in P0P register bit. At any time that BIOS or software is clearing PCS.PxE from 1 to 0, due to time needed for port staggering hardware process (up to 8 ports) to complete, BIOS and software shall delay the write to set the TM.PCD register by 1.4us. This bit is only applicable to project(s) that has port 0 physically.