Port Power Management Status Aand Control USB2 (PORTPMSC1) – Offset 484 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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xDCI MMIO Device
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xDCI PCI Configuration

Port Power Management Status Aand Control USB2 (PORTPMSC1) – Offset 484

USB2 PORTPMSC registers at offsets:
484h, 494h, ... (484h + (NumUSB2-1)*10h)

Bit Range	Default	Access	Field Name and Description
31:28	0h	RW/P	Port Test Control (PTC) When this field is ‘0’, the port is not operating in a test mode. (Default) A non-zero value indicates that the port is operating in test mode and the specific test mode is indicated by the specific value. A non-zero Port Test Control value is only valid to a port that is in the Disabled state. If the port is not in this state, the xHC shall respond with the Port Test Control field set to Port Test Control Error. The encoding of the Test Mode bits for a USB 2.0 port are: 0h: Test mode not enabled 1h: Test J_STATE 2h: Test K_STATE 3h: Test SE0_NAK 4h: Test Packet 5h: Test FORCE_ENABLE 6h–14h: Reserved. 15: Port Test Control Error
27:17	0h	RO	Rsvd1 (RSVD1) Reserved
16	0h	RW	Hardware LPM Enable (HLE) 0=disable 1=Enable. When this bit is a 1, hardware controlled LPM shall be enabled for this port. Refer to section 4 of the USB 2.0 LPM Specification for more information.
15:8	0h	RW/P	Device Address (DA) Note: This register is sticky.
7:4	0h	RW/P	Host Initiated Resume Duration (HIRD) Note: This register is sticky.
3	0h	RW/P	Remote Wake Enable (RWE) The host system sets this flag to enable or disable the device for remote wake from L1. 0=disable 1=enable The value of this flag will temporarily (while in L1) override the current setting of the Remote Wake feature set by the standard Set/ClearFeature() commands defined in Universal Serial Bus Specification, revision 2.0, Chapter 9.
2:0	0h	RW	L1 Status (L1S) Note: This register is sticky.

Port X Hardware LPM Control Register (PORTHLPMC1)

Port Status AndControl USB2 (PORTSC1) Port X Hardware LPM Control Register (PORTHLPMC1)