Power Control Enables (THC_CFG_PCE) – Offset a4 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Power Control Enables (THC_CFG_PCE) – Offset a4

Bit Range	Default	Access	Field Name and Description
31:6	0h	RO	Reserved (RSVD_31_6) Reserved.
5	0h	RW/V	Hardware Autonomous Enable (HAE) If set, then the PGCB may request a PG whenever it is idle. This bit is loaded with the value from the PowerGateEnable soft strap when the soft strap pull is complete.
4	0h	RW	Reserved (RSVD_4) Reserved.
3	1h	RW/V	Sleep Enable (SE) if clear, then IP will never asset Sleep to the retention flops. If set, then IP may assert Sleep during PG'ing. Note that some platforms may default this bit to 0, others to 1. The SE bit is RW only when the security policy is red unlock/Intel unlock. Otherwise the bit is RO.
2	0h	RW	D3-Hot Enable (D3HE) if set, then IP will PG when idle and the PMCSR[1:0] register in the IP = 11.
1	0h	RW	I3 Enable (I3E) if set, then IP will PG when idle and the D0i3 register (D0i3C[2] = 1) is set.
0	0h	RW	Software PowerGate Enable (SPE) Software PowerGate Enable: If this bit is set, the IP will PG when pmc_sw_pg_req_b =0. NOTE: PMCSR[1:0] must not be used for this condition. It may be any value and the IP must PG if this bit is set and it sees pmc_sw_pg_req_b asserted and IP has met its IDLE requirements for Power Gating. This is not a force power gate mechanism, rather a PMC assisted Hardware Autonomous.

UART Additional MMIO

Device Idle Power On Latency (THC_CFG_DEVIDLEPOL) UART Additional MMIO