Power Management 1 Enables and Status (PM1_EN_STS) – Offset 0 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Power Management 1 Enables and Status (PM1_EN_STS) – Offset 0

Bit Range	Default	Access	Field Name and Description
31	0h	RO	Reserved (RSVD_31) Reserved
30	0h	RW	PCI Express Wake Disable (PCIEXP_WAKE_DIS) This bit disables the inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register from waking the system. Modification of this bit has no impact on the value of the PCIEXP_WAKE_STS bit.
29:27	0h	RO	Reserved (RSVD_29_27) Reserved
26	0h	RW/V	RTC Alarm Enable (RTC_EN) This is the RTC alarm enable bit. It works in conjunction with the SCI_EN bit: RTC_EN SCI_EN Effect when RTC_STS is set 0 x No SMI# or SCI. If system was in S3-S5, no wake even occurs. 1 0 SMI#. If system was in S3-S5, then a wake event occurs before the SMI#. 1 1 SCI. If system was in S3-S5, then a wake event occurs before the SCI. Note: This bit is in the RTC well to allow an RTC event to wake after a power failure.
25	0h	RO	Reserved (RSVD_25) Reserved
24	0h	RW/V	Power Button Enable (PWRBTN_EN) This bit is the power button enable. It works in conjunction with the SCI_EN bit: PWRBTN_EN SCI_EN Effect when PWRBTN_STS is set 0 x No SMI# or SCI. 1 0 SMI#. 1 1 SCI. NOTE: PWRBTN_EN has no effect on the PWRBTN_STS bit being set by the assertion of the power button. The Power Button is always enabled as a Wake event.
23:22	0h	RO	Reserved (RSVD_23_22) Reserved
21	0h	RW	Global Enable (GBL_EN) The global enable bit. When both the GBL_EN and the GBL_STS are set, PCH generates an SCI.
20:17	0h	RO	Reserved (RSVD_20_17) Reserved
16	0h	RW	Timer Overflow Interrupt Enable (TMROF_EN) This is the timer overflow interrupt enable bit. It works in conjunction with the SCI_EN bit: TMROF_EN SCI_EN Effect when TMROF_STS is set 0 x No SMI# or SCI. 1 0 SMI#. 1 1 SCI.
15	0h	RW/1C/V	Wake Status (WAK_STS) This bit is set when the system is in one of the Sleep states (via the SLP_EN bit) and an enabled PCH Wake event occurs. Upon setting this bit, the PCH will transition the system to the ON state. This bit can only be set by hardware and can only be cleared by writing a one to this bit position. This bit is not affected by hard resets caused by a CF9 write, but is reset by RSMRST#. If a power failure occurs (such as removed batteries) without the SLP_EN bit set, the WAK_STS bit will not be set when the power returns if the AFTER_G3 bit is 0. If the AFTER_G3 bit is 1, then the WAK_STS bit will be set after waking from a power failure. If necessary, the BIOS can clear the WAK_STS bit in this case.
14	0h	RW/1C/V	PCI Express Wake Status (PCIEXP_WAKE_STS) This bit is set by hardware to indicate that the system woke due to a PCI Express wakeup event. This event can be caused by the PCI Express WAKE# pin being active, or one or more of the PCI Express ports being in beacon state, or recept of a PCI Express PME message at root port. This bit should only be set when one of these events causes the system to transition from a non-S0 system power state to the S0 system power state. This bit is set independant of the PCIEXP_WAKE_DIS bit. Software writes a 1 to clear this bit. If WAKE# pin is still active during the write or one or more PCI Express ports is in the beacon state or PME message received indication is not cleared in the root port, then the bit will remain active (i.e. all inputs to this bit are level sensitive) Note: This bit does not itself cause a wake event or prevent entry to a sleeping state. Thus if the bit is 1 and the system is put into a sleeping state, the system will not automatically wake.
13:12	0h	RO	Reserved (RSVD_13_12) Reserved
11	0h	RW/1C/V	Power Button Override (PWRBTNOR_STS) This bit is set any time a Power Button Override Event occurs (i.e. the power button is pressed for at least 4 consecutive seconds), the corresponding bit is received in the SMBus TCO message, the ME-Initiated Power Button Override bit is set, the ME-Initiated Host Reset with Power Down is set, or due to an internal thermal sensor catastrophic condition. These events cause an unconditional transition to the S5 state. The BIOS or SCI handler clears this bit by writing a 1 to it. This bit is not affected by hard resets via CF9h writes, and is not reset by RSMRST#. Thus, this bit is preserved through power failures. Note that this bit is still asserted when the global SCI_EN is set to '1' then an SCI will be generated.
10	0h	RW/1C/V	RTC Status (RTC_STS) This bit is set when the RTC generates an alarm (assertion of the IRQ8# signal), and is not affected by any other enable bit. See RTC_EN for the effect when RTC_STS goes active. This bit is only set by hardware and can only be reset by writing a one to this bit position. This bit is not affected by hard resets caused by a CF9 write, but is reset by DSW_PWROK.
9	0h	RO	Reserved (RSVD_9) Reserved
8	0h	RW/1C/V	Power Button Status (PWRBTN_STS) This bit is set when the PWRBTN# signal is asserted (low), independent of any other enable bit. See PWRBTN_EN for the effect when PWRBTN_STS goes active. PWRBTN_STS is always a wake event. This bit is only set by hardware and can be cleared by software writing a one to this bit position. This bit is not affected by hard resets caused by a CF9 write, but is reset by DSW_PWROK. If the PWRBTN# signal is held low for more than 4 seconds, the PCH clears the PWRBTN_STS bit, sets the PWRBTNOR_STS bit, the system transitions to the S5 state, and only PWRBTN# is enabled as a wake event. If PWRBTN_STS bit is cleared by software while the PWRBTN# pin is still held low, this will not cause the PWRBTN_STS bit to be set. The PWRBTN# signal must go inactive and active again to set the PWRBTN_STS bit. Note that the SMBus Unconditional Powerdown message, the CPU Thermal Trip and the Internal Thermal Sensors' Catastrophic Condition result in behavior matching the Powerbutton Override, which includes clearing this bit.
7:6	0h	RO	Reserved (RSVD_7_6) Reserved
5	0h	RW/1C/V	GBL Status (GBL_STS) This bit is set when an SCI is generated due to the BIOS wanting the attention of the SCI handler. BIOS has a corresponding bit, BIOS_RLS, which will cause an SCI and set this bit. The SCI handler should then clear this bit by writing a 1 to it. This bit will not cause wake events or SMI#. This bit is not effected by SCI_EN. Note: GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set. Software must take great care not to set the BIOS_RLS bit (which causes GBL_STS to be set) if the SCI handler is not in place.
4	0h	RW/1C/V	Bus Master Status (BM_STS) This bit is set to 1 by the PCH when a PCH-visible bus master requests access to memory or the BM_BUSY# signal is active. This bit is cleared by the CPU writing a 1 to this bit position. This bit will not cause a wake event, SCI, or SMI.
3:1	0h	RO	Reserved (RSVD_3_1) Reserved
0	0h	RW/1C/V	Timer Overflow Status (TMROF_STS) This is the timer overflow status bit. This bit gets set anytime bit 22 of the 24 bit timer goes low (bits are counted from 0 to 23). This will occur every 2.3435 seconds. See TMROF_EN for the effect when TMROF_STS goes active. Software clears this bit by writing a 1 to it.

Select Your Language

Using Intel.com Search

Quick Links

Recent Searches

Advanced Search

Only search in

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Power Management 1 Enables and Status (PM1_EN_STS) – Offset 0