Power Management Capabilities, Next Pointer And Capability ID (IDE_HOST_PMCAP_PMNP_PMCID) – Offset 50 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Power Management Capabilities, Next Pointer And Capability ID (IDE_HOST_PMCAP_PMNP_PMCID) – Offset 50

This register contains the power management capabilities, next pointer And capability ID values.

Bit Range	Default	Access	Field Name and Description
31:27	0h	RO	PME Support (PMES) This 5-bit field indicates the power states in which the function may assert PME#. A value of 0b for any bit indicates that the function is not capable of asserting the PME# signal while in that power state. bit(27) X XXX1b - PME# can be asserted from D0 bit(28) X XX1Xb - PME# can be asserted from D1 bit(29) X X1XXb - PME# can be asserted from D2 bit(30) X 1XXXb - PME# can be asserted from D3hot bit(31) 1 XXXXb - PME# can be asserted from D3cold
26	0h	RO	D2 Support (D2S) Hardwired to 0 to indicate that this device does not support D2
25	0h	RO	D1 Support (D1S) Hardwired to 0 to indicate that this device does not support D1
24:22	0h	RO	Aux Current (AUXC) Not implemented. Hardwired to 0.
21	1h	RO	Device Specific Initialization (DSI) indicates whether special initialization of this function is required (beyond the standard PCI configuration header) before the generic class device driver is able to use it. A 1 indicates that the function requires a device specific initialization sequence following transition to the D0 uninitialized state. Hardwired to 1 to indicate Device Specific Initialization is required.
20	0h	RO	Reserved (RSVD) Reserved.
19	0h	RO	PME Clock (PMECLK) Not implemented. Hardwired to 0.
18:16	3h	RO	Version (VER) Hardwired to value of 011b indicates that this function complies with rev 1.2 of PCI Power Management Interface Spec
15:8	0h	RO	Next Item Pointer (NP) Indicates the pointer for the next entry in the capabilities list. Hardwired to 0 to indicate no more linked list item.
7:0	1h	RO	Capability ID (CID) Hardwired to 01h to indicate the linked list item as the PCI Power Management registers