Power Management Configuration Reg 1 (PM_CFG) – Offset 1818 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Power Management Configuration Reg 1 (PM_CFG) – Offset 1818

Bit Range	Default	Access	Field Name and Description
31	0h	RW	SATA Interface Disable Indication (SATA_DIS_IND) When set to 1, this bit indicates that the SATA interface on the PCH is completely disabled. Therefore, the mPhy lanes normally assigned to SATA will operate through the PCIe controller (or not be used at all). When cleared, it indicates that at least some of the SATA interface lanes may be used actively in the PCH by the SATA controller, so none of the four lanes assigned to SATA interface can operate through the PCIe controller.
30	0h	RW	Timing t591 (TIMING_T591) This field configures t591 timing involved in the over-clocking flow (Wait times between writes from PMC to ICC registers when executing BCLK slow ramp flow) Note: Encodings are all min timings.
29	0h	RW	Allow 24MHz Crystal Oscillator Shutdown (ALLOW_24_OSC_SD) When this bit is '0', the 24MHz crystal oscillator will always be running while in S0. When this bit is '1', the 24MHz crystal oscillator may be shut down in S0 (Cx only) if all other conditions allow.
28	0h	RW	Time Sync Maximum Attempts (TS_MAXTRY) The value of this bit determines how many times the PMC will retry time synchronization before stopping and reporting failure to the initiator. Encoding: 0 Maximum of 5 attempts 1 Maximum of 10 attempts
27	0h	RO	Reserved
26	0h	RW	Boot Media RTD3 Power Management Enable (BMRTD3PME) 0: RTD3 is not enabled. Drive '1' to BOOTMPC pin 1: RTD3 is enabled. Drive the value of BMRTD3PP to BOOTMPC pin
25	0h	RW	Allow USB2 PHY Core Power Gating (ALLOW_USB2_CORE_PG) When this bit is '0' (default), USB2 PHY power gating is disabled. When this bit is '1', USB2 PHY power gating can occur if all other required conditions are met.
24	0h	RW/L	Energy Reporting Lock (ER_LOCK) When this bit is written to 1, it will remain 1 until the next host_prim_rst_b assertion. While this bit is 1, GEN_PMCON_A.ER_EN value cannot be changed. BIOS should write 1b1 to this bit only AFTER writing to GEN_PMCON_A.ER_EN.
23:22	0h	RO	Reserved
21	0h	RW	RTC Wake from DeepSx Disable (RTC_DSX_WAKE_DIS) When set, this bit disables RTC wakes from waking the system from DeepSx.
20	0h	RW	Boot Media RTD3 Reset Management Enable (BMRTD3RME) 0: Boot Media device not in D3. Drive '1' to reset pin 1: Boot Media device in D3. Drive the value of BMRTD3RP to reset pin
19:18	0h	RW/L	SLP_SUS# Minimum Assertion Width (SLP_SUS_MIN_ASST_WDTH) This 2-bit value indicates the minimum assertion width of the SLP_SUS# signal to guarantee that the SUS well power supplies have been fully power-cycled. This value may be modified per platform depending on power supply capacitance, board capacitance, power failure detection circuits, etc. Settings are: 00 = 0 ms (i.e. stretching disabled - default) 01 = 500ms 10 = 1s 11 = 4s This field is not writable when the SLP_Sx# Stretching Policy Lock- Down bit is set. This field is ignored when exiting a G3 state if the [quote]Disable SLP_X Stretching After SUS Power Failure[quote] bit is set. Note that unlike with all other SLP_* pin stretching, this disable bit only impacts SLP_SUS# stretching during G3 exit rather than both G3 and DeepSx exit. SLP_SUS# stretching always applies to DeepSx regardless of the disable bit. Programming Note: For platforms that enable DeepSx, BIOS must program SLP_SUS# stretching to be greater than or equal to the largest stretching value on any other SLP_* pin (SLP_S3#, SLP_S4#, SLP_LAN#, or SLP_A#). This bit is cleared by the rtc_pwrgood_rst_b pin.
17:16	0h	RW/L	SLP_A# Minimum Assertion Width (SLP_A_MIN_ASST_WDTH) This 2-bit value indicates the minimum assertion width of the SLP_A# signal to guarantee that the ASW power supplies have been fully power-cycled. This value may be modified per platform depending on power supply capacitance, board capacitance, power failure detection circuits, etc. Settings are: 00 = 0 ms (i.e. stretching disabled - default) 01 = 4 s 10 = 98 ms 11 = 2 s This field is not writable when the SLP_Sx# Stretching Policy Lock- Down bit is set. This field is ignored when exiting a G3 or DeepSx state if the [quote]Disable SLP_X Stretching After SUS Power Failure[quote] bit is set. This bit is cleared by the rtc_pwrgood_rst_b pin.
15:14	0h	RW/L	SLP_LAN# Minimum Assertion Width (SLP_LAN_MIN_ASST_WDTH) This 2-bit value indicates the minimum assertion width of the SLP_LAN# signal to guarantee that the power to the PHY has been fully power-cycled. This value may be modified per platform depending on power supply, capacitance, board capacitance, power failure detection circuits, etc. This field is not writable when the SLP_Sx# Stretching Policy Lock Down bit is set to [quote]1[quote].Encoding o0 : 0ms, 01: 1ms, 10: 50ms, 11: 2s
13	0h	RW	After G3 Last State Enable (AG3_LS_EN) When PM_CFG.AG3E is '0', AG3_LS_EN determines whether the PCH will consider the platform's previous state when determining whether to power-up after G3. Encodings: 0 (default): PCH power-up policies after G3 do not depend on the platform's state when the G3 occurred. 1: PCH power-up policies after G3 depend on the platform's state when the G3 occurred. - If the power failure occurred while the platform was in S0 or while in the process of going to S0, the platform will power-up to S0 upon exiting G3. - If the power failure occurred while the platform was in Sx or while in the process of going to Sx, the platform will stay in S4/S5 upon exiting G3. Note: This bit applies only when GEN_PMCON_3.AG3E is '0'. If AG3E is '1', the platform will always stay in S4/S5 after G3 regardless of the value of AG3_LS_EN.
12	0h	RW	After Type 8 Global Reset Last State Enable (A8GR_LS_EN) AGR_LS_EN determines whether the PCH will consider the platform's previous state when determining whether to power-up after non-thermal and non-explicitly requested type 8 global resets. Encodings: 0 (default): PCH power-up policies after a global reset do not depend on the platform's state when the reset occurred. 1: PCH power-up policies after a global reset depend on the platform's state when the reset occurred. If the global reset occurred while the platform was in S0 or while in the process of going to S0, the platform will power-up to S0 after the reset. If the global reset occurred while the platform was in Sx or while in the process of going to Sx, the platform will stay in S5 upon exiting G3.
11	0h	RW	Global Reset Three Strike Counter Enable (GR_TSC_EN) When set, GR_TSC_EN will cause the PMC to keep the platform in S5 after the third consecutive type 7 global reset occurs during the boot flow. The three strike counter is reset in the following situations: - The system reaches S0 - A type 8 global reset occurs, including after the three strike counter causes the system to stay in S5. - RSMRST# asserts (due to DeepSx entry or a G3 event occurring)
10	0h	RW	Power Button Debounce Mode (PB_DB_MODE) This bit controls when interrupts (SMI#, SCI) are generated in response to assertion of the PWRBTN# pin. This bit's values cause the following behavior: - '0': The 16ms debounce period applies to all usages of the PWRBTN# pin (legacy behavior). - '1': When a falling edge occurs on the PWRBTN# pin, an interrupt is generated and the 16ms debounce timer starts. Subsequent interrupts are masked while the debounce timer is running. Note: Power button override logic always samples the post-debounce version of the pin.
9:8	0h	RW/L	Reset Power Cycle Duration (PWR_CYC_DUR) The value in this register determines the minimum time a platform will stay in reset (SLP_S3#, SLP_S4#, SLP_S5# asserted and also SLP_A# and SLP_LAN# asserted if applicable) during a host partition reset with power cycle or a global reset. The duration programmed in this register takes precedence over the applicable SLP_# stretch timers in these reset scenarios. This field is not writable when the SLP_Sx# Stretching Policy Lock-Down bit is set.Encoding 00: 4-5sec, 01: 3-4sec, 10: 2-3 sec, 11: 1-2 sec Note that the duration programmed in this register should never be smaller than the stretch duration programmed in the following registers - - GEN_PMCON_3.SLP_S3_MIN_ASST_WDTH - GEN_PMCON_3.S4MAW - PM_CFG.SLP_A_MIN_ASST_WDTH - PM_CFG.SLP_LAN_MIN_ASST_WDTH
7:6	0h	RW	T37 Value (T37_VAL) This field determines the delay from ungating the CPU RTC clock until the PMC considers the clock to be valid, allowing the boot flow to proceed. Encodings: 00 - 10ms 01 - 5ms 10 - 1ms 11 - 200us
5	1h	RW/V	CPU OC Strap (COCS) SW programs this pin with the value that should be reflected to the GPIO8_OCS pin, when the pin is in native mode. Hardware also sets this bit when the over-clocking watchdog timer expires.
4:3	0h	RO	Reserved
2	0h	RW/L	Energy Reporting Enable (ER_EN) When this bit is 1, the PCH will periodically calculate and report its energy consumption to the CPU via PM_SYNC. When this bit is 0, the PCH will neither calculate nor report its energy consumption.
1:0	0h	RW/V	Timing t581 (TIMING_T581) This field configures the t581 timing involved in the power down flow (CPUPWRGD inactive to ICC_ICLK_INIT inactive). Encodings (all min timings): 00: 10 us (default) 01: 100 us 10: 1 ms 11: 10 ms reset_type=host_deep_rst_b