Power Management Control/Status (PM_CS) – Offset 74 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Power Management Control/Status (PM_CS) – Offset 74

Bit Range	Default	Access	Field Name and Description
15	0h	RW/1C	PME Status (PME_STATUS) This bit is set when the PCH XHC would normally assert the PME# signal independent of the state of the PME_En bit. Writing a 1 to this bit will clear it and cause the internal PME to deassert (if enabled). Writing a 0 has no effect. This bit must be explicitly cleared by the operating system each time the operating system is loaded.
14:13	0h	RO	Data Scale (DATA_SCALE) The PCH hardwires these bits to 00 because it does not support the associated Data register.
12:9	0h	RO	Data Select (DATA_SELECT) The PCH hardwires these bits to 0000 because it does not support the associated Data register.
8	0h	RW	PME Enable (PME_EN) A 1 enables the PCH XHC to generate an internal PME signal when PME_Status is 1. This bit must be explicitly cleared by the operating system each time it is initially loaded.
7:4	0h	RO	Reserved (RSVD) Reserved
3	1h	RW/L	No Soft Reset (NSR) No_Soft_Reset - When set ("1"), this bit indicates that devices transitioning from D3hot to D0 because of PowerState commands do not perform an internal reset. Configuration Context is preserved. Upon transition from the D3hot to the D0 Initialized state, no additional operating system intervention is required to preserve Configuration Context beyond writing the PowerState bits. Transition from D3hot to D0 by a system or bus segment reset will return to the device state D0 Uninitialized with only PME context preserved if PME is supported and enabled.
2	0h	RO	Reserved (RSVD2) Reserved
1:0	0h	RW	Power State (POWERSTATE) This 2-bit field is used both to determine the current power state of XHC function and to set a new power state. The definition of the field values are: 00b - D0 state 11b - D3hot state If software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally, however, the data is discarded and no state change occurs. When in the D3hot state, the PCH must not accept accesses to the XHC memory range, but the configuration space must still be accessible. Note: Software should wait for 100 ms before requesting the xHCI controller to re-enter D3 after a D3 exit.