Power Scheduler Control-0 (PWR_SCHED_CTRL0) – Offset 8140 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
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- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
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THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Power Scheduler Control-0 (PWR_SCHED_CTRL0) – Offset 8140

Power Scheduler Control-0

Bit Range	Default	Access	Field Name and Description
31:24	ffh	RW	Engine Idle Hysteresis (EIH) This register controls the min. idle span that has to be observed from the engine idle indicators before the power state flags (xhc_*_idle) will indicate a 1.
23:12	19h	RW	Backbone PLL Shutdown Advance Wake (BPSAW) This register controls the time before the next scheduled transaction where the Backbone PLL request will assert. Register Format: Bits [11:7] # of 125us uframes Bits [6:0] # of microseconds (0-124)
11:0	3ch	RW	Backbone PLL Shutdown Min. Idle Duration (BPSMID) The sum of this register plus the Backbone PLL Shutdown Advance Wake form to a Total Idle time. When the next scheduled periodic transaction is after present time + Total Idle, the Backbone PLL request will de-assert, allowing the PLL to shutdwon. Register Format: Bits [11:7] # of 125us uframes Bits [6:0] # of microseconds (0-124)

Bit Range

Default

Access

Field Name and Description

31:24

ffh

Engine Idle Hysteresis (EIH)

This register controls the min. idle span that has to be observed from the engine idle indicators before the power state flags (xhc_*_idle) will indicate a 1.

23:12

19h

Backbone PLL Shutdown Advance Wake (BPSAW)

This register controls the time before the next scheduled transaction where the Backbone PLL request will assert.
Register Format:
Bits [11:7] # of 125us uframes
Bits [6:0] # of microseconds (0-124)

11:0

3ch

Backbone PLL Shutdown Min. Idle Duration (BPSMID)

The sum of this register plus the Backbone PLL Shutdown Advance Wake form to a Total Idle time. When the next scheduled periodic transaction is after present time + Total Idle, the Backbone PLL request will de-assert, allowing the PLL to shutdwon. Register Format:
Bits [11:7] # of 125us uframes
Bits [6:0] # of microseconds (0-124)

Power Scheduler Control-1 (PWR_SCHED_CTRL2)

USB2 Port Link Control 4 (USB2_LINK_MGR_CTRL_REG4) Power Scheduler Control-1 (PWR_SCHED_CTRL2)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Power Scheduler Control-0 (PWR_SCHED_CTRL0) – Offset 8140