Power Scheduler Control-1 (PWR_SCHED_CTRL2) – Offset 8144 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Power Scheduler Control-1 (PWR_SCHED_CTRL2) – Offset 8144

These bit enable by EP type those EPs classes that are considered for determining next periodic active interval for pre-wake of
the periodic_active signal. EP classes that are disabled may never be observed in setting of the periodic_active signal.

Bit Range	Default	Access	Field Name and Description
31:27	0h	RW	Reserved (RSVD0) Reserved
26:24	0h	RO	Reserved
23:21	0h	RW	Reserved (RSVD1) Reserved
20:10	0h	RO	Reserved
9	1h	RW	HS Interrupt-OUT Alarm (HS_INT_OUT_ALRM) HS Interrupt OUT Alarm
8	0h	RW	HS Interrupt-IN Alarm (HS_INT_IN_ALRM) HS Interrupt IN Alarm (HSII): Note: This is required to be set to enable the functionality behind the PCICFG.HSCFG2.HSIIPAPC method of tracking HS Intr IN EP's for Periodic Active.
7	0h	RW	SS Interrupt-OUT FC Alarm (SS_INT_OUT_FC_ALRM) SS Interrupt OUT Alarm
6	0h	RW	SS Interrupt-IN Alarm (SS_INT_IN_FC_ALRM) SS Interrupt IN Alarm
5	1h	RW	SS Interrupt-OUT and not in FC Alarm (SS_INT_OUT_ALRM) SS Interrupt OUT and not in FC Frame Alarm
4	1h	RW	SS Interrupt-IN and not in FC Alarm (SS_INT_IN_ALRM) SS Interrupt IN and not in FC Frame Alarm
3	1h	RW	HS ISO-OUT Alarm (HS_ISO_OUT_ALRM) HS ISO-OUT Alarm
2	1h	RW	HS ISO-IN Alarm (HS_ISO_IN_ALRM) HS ISO-IN Alarm
1	1h	RW	SS ISO-OUT Alarm (SS_ISO_OUT_ALRM) SS ISO-OUT Alarm
0	1h	RW	SS ISO-IN Alarm (SS_ISO_IN_ALRM) SS ISO-IN Alarm

AUX Power Management Control (AUX_CTRL_REG2)

Power Scheduler Control-0 (PWR_SCHED_CTRL0) AUX Power Management Control (AUX_CTRL_REG2)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Power Scheduler Control-1 (PWR_SCHED_CTRL2) – Offset 8144