Power Transition Delay Control (PTDC) – Offset 1e28 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Power Transition Delay Control (PTDC) – Offset 1e28

Bit Range	Default	Access	Field Name and Description
31	0h	RW	SRAM Bit Line Float Disable (SBLFD) When set, it disables the SRAM bit line float signal assertion during SRAM retention state.This bit do not impact LDO retention state entry after the SRAM retention idle time-out.
30	0h	RW	SRAM Sleep Disable (SSLPD) When set, it disables the SRAM sleep signal assertion during SRAM retention state.This bit do not impact LDO retention state entry after the SRAM retention idle time-out.
29:26	0h	RO	Reserved
25:23	0h	RW	SRAM Power Gating Staggering (SPGS) Register is used to control the SRAM staggering needs when transitioning between power gating mode and active mode.000: Disabled (relies on SRAM PFET daisy chain).001: 1 SRAM functional clock.010: 2 SRAM functional clocks.011: 4 SRAM functional clocks.100: 8 SRAM functional clocks....111: 64 SRAM functional clocks.
22:20	1h	RW	SRAM Wake Latency (SWL) Specifies the time needed for the SRAM EBB to wake up from firewall removal / retention state before allowing the SRAM access to take place. 000: 1 SRAM functional clock001: 2 SRAM functional clocks010: 4 SRAM functional clocks011: 8 SRAM functional clocks...111: 128 SRAM functional clocks
19:16	0h	RW	Power FET On Delay (PFOL) Specifies the time needed for the PGD to ramp up after PFET is turned on, before de-asserting the firewall. 0000: Disabled (relies on PFET ack)0001 - 1111: 1 - 15 AON ROSC clocksThe delay value will also indirectly affecting the SRAM power on staggering delay accordingly.Implementation Note: As a safety time-out feature, the HW may ignore the PFET ack if it takes longer time than 4x the ramp up time specified in this register.
15:12	4h	RW	IOSF Power Gating Idle Wait (IPGIW) Specifies the time needed for the IOSF ISM to stay idle before initiating power gating. The actual clock count is 2 ^ IPGIW.0000: 1 AON ROSC clocks0001: 2 AON ROSC clocks0010: 4 AON ROSC clocks0011: 8 AON ROSC clocks...1111: 32768 AON ROSC clocks
11:9	0h	RW	Allowed Exit Time Power Management Threshold (AETPMT) Specifies the AET threshold needed before allowing any power management that could increase the response latency. HW only allow PG (similar to D0i3) if the AET value this threshold. 000: 1 s001: 4 s010: 16 s011: 64 s100: 256 us101: 1 ms110 - 111: reserved
8:7	0h	RO	Reserved
6:4	0h	RW	SRAM Retention Mode Idle Wait (SRMIW) Specifies the time needed for the SRAM access path to stay idle before initiating SRAM retention mode entry.000: 4 AON ROSC clocks001: 8 AON ROSC clocks010: 16 AON ROSC clocks011: 32 AON ROSC clocks100: 64 AON ROSC clocks101: 128 AON ROSC clocks110: 256 AON ROSC clocks111: 512 AON ROSC clocks
3:2	1h	RW	SRAM Retention Mode Staggering (SRMS) Register is used to control the SRAM staggering needs when transitioning between retention mode and active mode.00: Disabled.01: 1 SRAM functional clock.10: 2 SRAM functional clocks.11: 3 SRAM functional clocks.
1:0	0h	RO	Reserved