Receive Buffer (RBR) – Offset 0 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
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Integrated Sensor Hub (ISH) PCI Configuration
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Intel(R) Management Engine Interface (MEI) PCI Configuration
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- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
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SATA Port 7 ABAR
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SPI PCI Configuration
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- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
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THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Receive Buffer (RBR) – Offset 0

Receive Buffer Register. RBR mode is only available when LCR register [7] (DLAB bit) = 0.

Bit Range	Default	Access	Field Name and Description
31:8	0h	NA	Res_rbr (Res_rbr) Reserved
7:0	0h	RO	rbr (rbr) Data byte received on the serial input port (sin) in UART mode. The data in this register is valid only if the Data Ready (DR) bit in the Line Status Register (LCR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an over-run error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO is preserved, but any incoming data are lost and an over-run error occurs.

Bit Range

Default

Access

Field Name and Description

31:8

Res_rbr (Res_rbr)

Reserved

7:0

rbr (rbr)

Data byte received on the serial input port (sin) in UART mode. The data in this register is valid only if the Data Ready (DR) bit in the Line Status Register (LCR) is set.
If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an over-run error.
If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO is preserved, but any
incoming data are lost and an over-run error occurs.

Interrupt Enable (IER)

Transmit Holding (THR) Interrupt Enable (IER)