REG ACTIVELTR (ACTIVELTR) – Offset 2bc - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

REG ACTIVELTR (ACTIVELTR) – Offset 2bc

ACTIVELTR_VALUEs

Bit Range	Default	Access	Field Name and Description
31	0h	RO	Non_Snoop_Requirment (Non_Snoop_Requirment) Non_Snoop_Requirment (non_snoop_requirment) If the Requirement (bit 31) is clear, that indicates that the device has no LTR requirement for this type of traffic (i.e. it can wait for service indefinitely). If the 10- bit latency value is zero it indicates that the device cannot tolerate any delay and needs the best possible service/response time.
30:29	0h	RO	RESERVED (RESERVED0) Reserved
28:26	0h	RO	Non_Snoop_latency_scale (Non_Snoop_latency_scale) Non_Snoop_latency_scale (non_snoop_latency_scale) Support for codes 010 (1us) or 011 (32us) for Snoop Latency Scale (1us -) 32ms total span) only. Writes to this CSR which dont match those values will be dropped completely, next read will return previous value.
25:16	0h	RO	Non_Snoop_value (Non_Snoop_value) Non_Snoop_value (non_snoop_value) 10-bit latency value
15	0h	RW	snoop_requirment (snoop_requirment) Snoop_Requirment (snoop_requirment) If the Requirement (bit 15) is clear, that indicates that the device has no LTR requirement for this type of traffic (i.e. it can wait for service indefinitely). If the 10- bit latency value is zero it indicates that the device cannot tolerate any delay and needs the best possible service/response time.
14:13	0h	RO	Reserved (Reserved1) Reserved
12:10	2h	RW	Snoop_latency_scale (Snoop_latency_scale) Snoop_latency_scale (snoop_latency_scale) Support for codes 010 (1us) or 011 (32us) for Snoop Latency Scale(1us -) 32ms total span) only. Writes to this CSR which dont match those values will be dropped completely, next read will return previous value.
9:0	0h	RW	snoop_value (snoop_value) Snoop_value (snoop_value) 10-bit latency value

REG IDLELTR (IDLELTR)

REG GENERAL (GENERAL) REG IDLELTR (IDLELTR)