REG GENERAL (GENERAL) – Offset 2b8 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

REG GENERAL (GENERAL) – Offset 2b8

General Register

Bit Range	Default	Access	Field Name and Description
31:28	0h	RO	Reserved (Reserved0) Reserved
27	0h	RW	i3c1_sda_out_mux_sel (i3c1_sda_out_mux_sel) i3c1_sda_out_mux_sel 1 = SW override, 0 = native mode
26	0h	RW	i3c0_sda_out_mux_sel (i3c0_sda_out_mux_sel) i3c0_sda_out_mux_sel 1 = SW override, 0 = native mode
25	0h	RW	i3c1_sda_out_signal_state (i3c1_sda_out_signal_state) i3c1_sda_out_signal_state sda line control from SW reg (0 - high impedance, 1 - output driver enabled (drives low))
24	0h	RW	i3c0_sda_out_signal_state (i3c0_sda_out_signal_state) i3c0_sda_out_signal_state sda line control from SW reg (0 - high impedance, 1 - output driver enabled (drives low))
23	0h	RW	i3c1_scl_out_mux_sel (i3c1_scl_out_mux_sel) i3c1_scl_out_mux_sel 1= SW override, 0 = native mode
22	0h	RW	i3c0_scl_out_mux_sel (i3c0_scl_out_mux_sel) i3c0_scl_out_mux_sel 1= SW override, 0 = native mode
21	0h	RW	i3c1_scl_out_signal_state (i3c1_scl_out_signal_state) i3c1_scl_out_signal_state scl line control from SW reg (0 - high impedance, 1 - output driver enabled (drives low))
20	0h	RW	i3c0_scl_out_signal_state (i3c0_scl_out_signal_state) i3c0_scl_out_signal_state scl line control from SW reg (0 - high impedance, 1 - output driver enabled (drives low))
19	0h	RW	i3c1_sda_oe_mux_sel (i3c1_sda_oe_mux_sel) i3c1_sda_oe_mux_sel 1 = SW override, 0 = native mode
18	0h	RW	i3c0_sda_oe_mux_sel (i3c0_sda_oe_mux_sel) i3c0_sda_oe_mux_sel 1 = SW override, 0 = native mode
17	0h	RW	i3c1_sda_oe_signal_state (i3c1_sda_oe_signal_state) i3c1_sda_oe_signal_state sda line control from SW reg (0 - high impedance, 1 - output driver enabled (drives low))
16	0h	RW	i3c0_sda_oe_signal_state (i3c0_sda_oe_signal_state) i3c0_sda_oe_signal_state sda line control from SW reg (0 - high impedance, 1 - output driver enabled (drives low))
15	0h	RW	i3c1_scl_oe_mux_sel (i3c1_scl_oe_mux_sel) i3c1_scl_oe_mux_sel 1= SW override, 0 = native mode
14	0h	RW	i3c0_scl_oe_mux_sel (i3c0_scl_oe_mux_sel) i3c0_scl_oe_mux_sel 1= SW override, 0 = native mode
13	0h	RW	i3c1_scl_oe_signal_state (i3c1_scl_oe_signal_state) i3c1_scl_oe_signal_state scl line control from SW reg (0 - high impedance, 1 - output driver enabled (drives low))
12	0h	RW	i3c0_scl_oe_signal_state (i3c0_scl_oe_signal_state) i3c0_scl_oe_signal_state scl line control from SW reg (0 - high impedance, 1 - output driver enabled (drives low))
11	0h	RO	i3c1_sda_out_rd_drive (i3c1_sda_out_rd_drive) i3c1_sda_out_rd_drive scl line control from IP (0 - high impedance, 1 - output driver enabled (drives low))
10	0h	RO	i3c0_sda_out_rd_drive (i3c0_sda_out_rd_drive) i3c0_sda_out_rd_drive scl line control from IP (0 - high impedance, 1 - output driver enabled (drives low))
9	0h	RO	i3c1_scl_out_rd_drive (i3c1_scl_out_rd_drive) i3c1_scl_out_rd_drive scl line state (0 - output drives low, 1 - high impedance)
8	0h	RO	i3c0_scl_out_rd_drive (i3c0_scl_out_rd_drive) i3c0_scl_out_rd_drive scl line state (0 - output drives low, 1 - high impedance)
7	0h	RO	i3c1_sda_rd_pre_drive (i3c1_sda_rd_pre_drive) i3c1_sda_rd_pre_drive sda line control from IP (0 - high impedance, 1 - output driver enabled (drives low))
6	0h	RO	i3c0_sda_rd_pre_drive (i3c0_sda_rd_pre_drive) i3c0_sda_rd_pre_drive sda line control from IP (0 - high impedance, 1 - output driver enabled (drives low))
5	1h	RO	i3c1_sda_rd_post_drive (i3c1_sda_rd_post_drive) i3c1_sda_rd_post_drive sda line state (0 - input driven low, 1 - input driven high)
4	1h	RO	i3c0_sda_rd_post_drive (i3c0_sda_rd_post_drive) i3c0_sda_rd_post_drive sda line state (0 - input driven low, 1 - input driven high)
3	0h	RO	i3c1_scl_rd_pre_drive (i3c1_scl_rd_pre_drive) i3c1_scl_rd_pre_drive scl line control from IP (0 - high impedance, 1 - output driver enabled (drives low))
2	0h	RO	i3c0_scl_rd_pre_drive (i3c0_scl_rd_pre_drive) i3c0_scl_rd_pre_drive scl line control from IP (0 - high impedance, 1 - output driver enabled (drives low))
1	1h	RO	i3c1_scl_rd_post_drive (i3c1_scl_rd_post_drive) i3c1_scl_rd_post_drive scl line state (0 - input driven low, 1 - input driven high)
0	1h	RO	i3c0_scl_rd_post_drive (i3c0_scl_rd_post_drive) i3c0_scl_rd_post_drive scl line state (0 - input driven low, 1 - input driven high)

Select Your Language

Using Intel.com Search

Quick Links

Recent Searches

Advanced Search

Only search in

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

REG GENERAL (GENERAL) – Offset 2b8