REG RESETS (RESETS) – Offset 2b4 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

REG RESETS (RESETS) – Offset 2b4

Soft reset register

Bit Range	Default	Access	Field Name and Description
31:2	0h	RO	Reserved0 (Reserved0) RESETS register Reserved bits
1	0h	RW	i3c_reset_done (i3c_reset_done) Status indicating completion of Reset operation to I3C IPs and DMA. Will be polled by SW. Will clear when I3C reset bit is set to 0. Convergence layer should use write pulse to the I3C reset register bit to clear this register.
0	0h	RW	i3c_reset (i3c_reset) Resets LPSS I3C Controller 0, Controller 1 and the DMA Controller at one shot. HW will guarantee there are no outstanding completions in the PSF and/or OCP fabric before resetting. 1 => out of reset 0 => reset asserted Note : SW must program 1 during intiailisation (prior to driver accessing MMIO space) to ensure the I3C HCIs are accessible.

Bit Range

Default

Access

Field Name and Description

31:2

Reserved0 (Reserved0)

RESETS register Reserved bits

i3c_reset_done (i3c_reset_done)

Status indicating completion of Reset operation to I3C IPs and DMA. Will be polled by SW. Will clear when I3C reset bit is set to 0. Convergence layer should use write pulse to the I3C reset register bit to clear this register.

i3c_reset (i3c_reset)

Resets LPSS I3C Controller 0, Controller 1 and the DMA Controller at one shot. HW will guarantee there are no outstanding completions in the PSF and/or OCP fabric before resetting.
1 => out of reset
0 => reset asserted
Note : SW must program 1 during intiailisation (prior to driver accessing MMIO space) to ensure the I3C HCIs are accessible.

REG GENERAL (GENERAL)

REG VND_SPEC_EXT_CAP_2 (VND_SPEC_EXT_CAP_2) REG GENERAL (GENERAL)